MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 572

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Memory map and register descriptions
27.4.2 Flash Bank 0 Control Register (FMC_PFB0CR)
Address: FMC_PFB0CR is 4001_F000h base + 4h offset = 4001_F004h
572
Reset
Reset
CLCK_WAY[3:0]
CINV_WAY[3:0]
B0RWSC[3:0]
Bit
Bit
W
W
R
R
31–28
27–24
23–20
Field
Field
31
15
0
0
B0RWSC[3:0]
30
14
0
0
10
11
Bank 0 Read Wait State Control
This read-only field defines the number of wait states required to access the bank 0 flash memory.
The relationship between the read access time of the flash array (expressed in system clock cycles) and
RWSC is defined as:
Access time of flash array [system clocks] = RWSC + 1
The FMC automatically calculates this value based on the ratio of the system clock speed to the flash
clock speed. For example, when this ratio is 4:1, the field's value is 3h.
Cache Lock Way x
These bits determine if the given cache way is locked such that its contents will not be displaced by future
misses.
The bit setting definitions are for each bit in the field.
0
1
Cache Invalidate Way x
These bits determine if the given cache way is to be invalidated (cleared). When a bit within this field is
written, the corresponding cache way is immediately invalidated: the way's tag, data, and valid contents
are cleared. This field always reads as zero.
Cache way is unlocked and may be displaced
Cache way is locked and its contents are not displaced
Only write accesses may be performed by this master
Both read and write accesses may be performed by this master
29
13
1
0
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
FMC_PFAPR field descriptions (continued)
28
12
1
0
0
27
11
0
0
FMC_PFB0CR field descriptions
CLCK_WAY[3:0]
Table continues on the next page...
26
10
0
0
25
0
0
9
24
0
0
8
Description
Description
23
0
0
7
CRC[2:0]
CINV_WAY[3:0]
22
0
0
6
0
21
0
0
5
20
0
1
4
Freescale Semiconductor, Inc.
S_B_
INV
19
0
0
1
3
B0MW[1:0]
18
0
1
2
17
1
1
1
16
0
0
1
0