MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 82

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

System modules
3.3.8.1 Number of peripheral bridges
This device contains two identical peripheral bridges.
3.3.8.2 Memory maps
The peripheral bridges are used to access the registers of most of the modules on this
device. See
assignment for each module.
3.3.8.3 MPRA register
Each of the two peripheral bridges supports up to 8 crossbar switch masters, each
assigned to a MPROTx field in the MPRA register. However, fewer are supported on this
device. See
3.3.8.4 AIPS_Lite MPRA register reset value
Therefore, masters 0, 1, and 2 are trusted bus masters after reset.
82
System memory map
• AIPSx_MPRA reset value is 0x7770_0000
Crossbar switch
Full description
Clocking
Topic
AIPS0 Memory Map
Crossbar switch
Table 3-22. Reference links to related information
Peripheral bridge
Related module
Crossbar switch
Figure 3-12. Peripheral bridge configuration
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
(AIPS-Lite)
Transfers
for details of the master port assignments for this device.
and
peripheral bridge
AIPS1 Memory Map
AIPS-Lite
Peripheral bridge (AIPS-Lite)
System memory map
Transfers
Clock Distribution
Crossbar switch
Reference
for the memory slot
Freescale Semiconductor, Inc.