MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 380

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

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Memory map/register definition
19.2.3 Peripheral Access Control Register (AIPSx_PACRn)
Each of the peripherals has a four-bit PACR[0:127] field which defines the access levels
supported by the given module. Eight PACR fields are grouped together to form a 32-bit
PACR[A:P] register:
The peripheral assignments to each PACR register is defined by the memory map slot
that the peripherals are assigned.See the device's Memory Map details for the
assignments for your particular device.
380
• PACRA-P define the access levels for the 128 peripherals
Reserved
WP7
Field
SP7
TP6
TP7
4
3
2
1
0
Trusted protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates .
0
1
This read-only field is reserved and always has the value zero.
Supervisor protect
Determines whether the peripheral requires supervisor privilege level for access. When this bit is set, the
master privilege level must indicate the supervisor access attribute , and the MPROTn[MPL] control bit for
the master must be set. If not, access terminates with an error response and no peripheral access
initiates .
0
1
Write protect
Determines whether the peripheral allows write accesss. When this bit is set and a write access is
attempted, access terminates with an error response and no peripheral access initiates.
0
1
Trusted protect
Determines whether the peripheral allows accesses from an untrusted master. When this bit is set and an
access is attempted by an untrusted master, the access terminates with an error response and no
peripheral access initiates.
0
1
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
This peripheral does not require supervisor privilege level for accesses.
This peripheral requires supervisor privilege level for accesses.
This peripheral allows write accesses.
This peripheral is write protected.
Accesses from an untrusted master are allowed.
Accesses from an untrusted master are not allowed.
AIPSx_PACRn field descriptions (continued)
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Description
Freescale Semiconductor, Inc.

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