MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 401

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

The transfer-control descriptor local memory is further partitioned into:
Freescale Semiconductor, Inc.
Address path
Data path
Program model/channel arbitration
Control
Submodule
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 21-1. eDMA engine submodules
This block implements registered versions of two channel
transfer control descriptors, channel x and channel y, and
manages all master bus-address calculations. All the
channels provide the same functionality. This structure allows
data transfers associated with one channel to be preempted
after the completion of a read/write sequence if a higher
priority channel activation is asserted while the first channel
is active. After a channel is activated, it runs until the minor
loop is completed, unless preempted by a higher priority
channel. This provides a mechanism (enabled by
DCHPRIn[ECP]) where a large data move operation can be
preempted to minimize the time another channel is blocked
from execution.
When any channel is selected to execute, the contents of its
TCD are read from local memory and loaded into the address
path channel x registers for a normal start and into channel y
registers for a preemption start. After the minor loop
completes execution, the address path hardware writes the
new values for the TCDn_{SADDR, DADDR, CITER} back to
local memory. If the major iteration count is exhausted,
additional processing is performed, including the final
address pointer updates, reloading the TCDn_CITER field,
and a possible fetch of the next TCDn from memory as part
of a scatter/gather operation.
This block implements the bus master read/write datapath. It
includes 16 bytes of register storage and the necessary
multiplex logic to support any required data alignment. The
internal read data bus is the primary input, and the internal
write data bus is the primary output.
The address and data path modules directly support the 2-
stage pipelined internal bus. The address path module
represents the 1st stage of the bus pipeline (address phase),
while the data path module implements the 2nd stage of the
pipeline (data phase).
This block implements the first section of the eDMA
programming model as well as the channel arbitration logic.
The programming model registers are connected to the
internal peripheral bus. The eDMA peripheral request inputs
and interrupt request outputs are also connected to this block
(via control logic).
This block provides all the control functions for the eDMA
engine. For data transfers where the source and destination
sizes are equal, the eDMA engine performs a series of
source read/destination write operations until the number of
bytes specified in the minor loop byte count has moved. For
descriptors where the sizes are not equal, multiple accesses
of the smaller size data are required for each reference of the
larger size. As an example, if the source size references 16-
bit data and the destination is 32-bit data, two reads are
performed, then one 32-bit write.
Chapter 21 Direct Memory Access Controller (eDMA)
Function
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