MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 736

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

CMP Functional Description
32.8.2.2 Stop Mode Operation
Subject to platform-specific clock restrictions, the MCU is brought out of stop when a
compare event occurs and the corresponding interrupt is enabled. Similarly, if CR1[OPE]
is enabled, the comparator output operates as in the normal operating mode and
comparator output is placed onto the external pin. In stop modes, the comparator can be
operational in both high speed (HS) comparison mode (CR1[PMODE] = 1) and low
speed (LS) comparison mode (CR1[PMODE] = 0), but it is recommended to use the low
speed mode to minimize power consumption.
If stop is exited with a reset, all comparator registers are put into their reset state.
32.8.2.3 Low-Leakage Mode Operation
When the chip is in low-leakage modes, the CMP module is partially functional and is
limited to low speed mode (regardless of the CR1[PMODE] bit's setting). Windowed,
sampled, and filtered modes are not supported. The CMP output pin is latched and does
not reflect the compare output state.
The positive- and negative-input voltage can be from external pins or the DAC output.
The MCU can be brought out of the low-leakage mode if a compare event occurs and the
CMP interrupt is enabled. After wakeup from low-leakage modes, the CMP module is in
the reset state except for the SCR[CFF] and SCR[CFR] flags.
32.8.3 Startup and Operation
A typical startup sequence is as follows.
The time required to stabilize COUT will be the power-on delay of the comparators plus
the largest propagation delay from a selected analog source through the analog
comparator, windowing function and filter. Power on delay of the comparators are
available from data sheets. The windowing function has a maximum of 1 bus clock
period delay. Filter delay is specified in
Low Pass
Filter.
During operation, the propagation delay of the selected data paths must always be
considered. It can take many bus clock cycles for COUT and the CFR/CFF status bits to
reflect an input change or a configuration change to one of the components involved in
the data path.
When programmed for filtering modes, COUT will initially be equal to zero until
sufficient clock cycles have elapsed to fill all stages of the filter. This occurs even if
COUTA is at a logic one.
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
736
Freescale Semiconductor, Inc.