MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 529

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Chapter 24 Multipurpose Clock Generator (MCG)
24.4.1.2 MCG Mode Switching
The C1[IREFS] bit can be changed at any time, but the actual switch to the newly
selected reference clocks is shown by the S[IREFST] bit. When switching between
engaged internal and engaged external modes, the FLL will begin locking again after the
switch is completed.
The C1[CLKS] bits can also be changed at anytime, but the actual switch to the newly
selected clock is shown by the S[CLKST] bits. If the newly selected clock is not
available, the previous clock will remain selected.
The C4[DRST_DRS] write bits can be changed at anytime except when C2[LP] bit is 1.
If the C4[DRST_DRS] write bits are changed while in FLL engaged internal (FEI) or
FLL engaged external (FEE), the MCGOUTCLK will switch to the new selected DCO
range within three clocks of the selected DCO clock. After switching to the new DCO,
the FLL remains unlocked for several reference cycles. DCO startup time is equal to the
FLL acquisition time. After the selected DCO startup time is over, the FLL is locked. The
completion of the switch is shown by the C4[DRST_DRS] read bits.
24.4.2 Low Power Bit Usage
The C2[LP] bit is provided to allow the FLL or PLL to be disabled and thus conserve
power when these systems are not being used. The C4[DRST_DRS] can not be written
while C2[LP] bit is 1. However, in some applications, it may be desirable to enable the
FLL or PLL and allow it to lock for maximum accuracy before switching to an engaged
mode. Do this by writing C2[LP] to 0.
24.4.3 MCG Internal Reference Clocks
This module supports two internal reference clocks with nominal frequencies of 32 kHz
(slow IRC) and 4 MHz (fast IRC).
24.4.3.1 MCG Internal Reference Clock
The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other on-
chip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is
driven by either the fast internal reference clock (2 MHz IRC) or the slow internal
reference clock (32 kHz IRC). The IRCS clock frequency can be re-targeted by trimming
the period of its IRCS selected internal reference clock. This can be done by writing a
new trim value to the C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.
529