MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 906

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
edge is detected, that is, the edge selected by ELS(n)B:ELS(n)A bits. The CH(n+1)F bit
is set when the second rising edge is detected, that is, the edge selected by ELS(n
+1)B:ELS(n+1)A bits. The CH(n+1)F bit indicates when two edges of the period were
captured and the C(n)V and C(n+1)V registers are ready for reading.
36.4.24.5 Read Coherency Mechanism
The dual edge capture mode implements a read coherency mechanism between the FTM
counter value captured in C(n)V and C(n+1)V registers. The read coherency mechanism
is illustrated in the following figure. In this example, the channels (n) and (n+1) are in
dual edge capture – continuous mode for positive polarity pulse width measurement.
Thus, the channel (n) is configured to capture the FTM counter value when there is a
rising edge at channel (n) input signal, and channel (n+1) to capture the FTM counter
value when there is a falling edge at channel (n) input signal.
906
Figure 36-248. Dual Edge Capture – Continuous Mode to Measure of the Period Between
Note
- The commands set DECAPEN, set DECAP, clear CH(n)F, and clear CH(n+1)F are made by the user.
channel (n) input
DECAPEN bit
(after the filter
channel input)
CH(n+1)F bit
DECAP bit
FTM counter
CH(n)F bit
C(n+1)V
C(n)V
clear CH(n+1)F
set DECAPEN
clear CH(n)F
set DECAP
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K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
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Two Consecutive Rising Edges
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