MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 966

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

CMT Interrupts and DMA
MSC[EOCF] is set when:
In the case where MSC[MCGEN] bit is cleared and then set before the end of the
modulation cycle, MSC[EOCF] bit will not be set when MSC[MCGEN] is set, but will
become set at the end of the current modulation cycle.
When MSC[MCGEN] becomes disabled, the CMT module does not set the EOC flag at
the end of the last modulation cycle.
If MSC[EOCIE] bit is high when MSC[EOCF] bit is set, the CMT module will generate
an interrupt request or a DMA transfer request.
MSC[EOCF] bit must be cleared to prevent from being generated another event (interrupt
or DMA request) after exiting the service routine. See following table.
The EOC interrupt is coincident with loading the down-counter with the contents of
CMD1:CMD2 and loading the space period register with the contents of CMD3:CMD4.
The EOC interrupt provides a means for the user to reload new mark/space values into
the modulator data registers. Modulator data register updates will take effect at the end of
the current modulation cycle. Note that the down-counter and space period register are
updated at the end of every modulation cycle, irrespective of interrupt handling and the
state of the EOCF flag.
966
DMA[DM
• The modulator is not currently active and MSC[MCGEN] bit is set to begin the
• At the end of each modulation cycle (when the counter is reloaded from
A]
0
1
initial CMT transmission
CMD1:CMD2) while MSC[MCGEN] bit is set
MSC[EOCIE]
X
X
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 39-19. How to clear MSC[EOCF] bit
MSC[EOCF] bit is cleared by reading the CMT modulator status and control register
MSC followed by an access of CMD2 or CMD4.
MSC[EOCF] bit is cleared by the CMT DMA transfer done.
Description
Freescale Semiconductor, Inc.