MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 9

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Section Number
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
9.9
9.10
9.11
9.12
9.13
9.14
9.15
10.1
Freescale Semiconductor, Inc.
Introduction...................................................................................................................................................................191
9.1.1
The Debug Port.............................................................................................................................................................193
9.2.1
9.2.2
Debug Port Pin Descriptions.........................................................................................................................................195
System TAP connection................................................................................................................................................195
9.4.1
JTAG status and control registers.................................................................................................................................196
9.5.1
9.5.2
Debug Resets................................................................................................................................................................200
AHB-AP........................................................................................................................................................................201
ITM...............................................................................................................................................................................202
Core Trace Connectivity...............................................................................................................................................202
Embedded Trace Macrocell v3.5 (ETM)......................................................................................................................202
Coresight Embedded Trace Buffer (ETB)....................................................................................................................203
9.11.1
9.11.2
TPIU..............................................................................................................................................................................204
DWT.............................................................................................................................................................................204
Debug in Low Power Modes........................................................................................................................................205
9.14.1
Debug & Security.........................................................................................................................................................206
Introduction...................................................................................................................................................................207
References....................................................................................................................................................193
JTAG-to-SWD change sequence.................................................................................................................194
JTAG-to-cJTAG change sequence...............................................................................................................194
IR Codes.......................................................................................................................................................195
MDM-AP Control Register..........................................................................................................................197
MDM-AP Status Register............................................................................................................................199
Performance Profiling with the ETB...........................................................................................................203
ETB Counter Control...................................................................................................................................204
Debug Module State in Low Power Modes.................................................................................................206
Signal Multiplexing and Signal Descriptions
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Chapter 10
Chapter 9
Debug
Title
Page
9