MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 562

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MK30DN512ZVLK10

Manufacturer Part Number
MK30DN512ZVLK10
Description
ARM Microcontrollers - MCU KINETIS 512K SLCD
Manufacturer
Freescale Semiconductor
Datasheet

Specifications of MK30DN512ZVLK10

Core
ARM Cortex M4
Processor Series
K30
Data Bus Width
32 bit
Maximum Clock Frequency
50 MHz
Program Memory Size
512 KB
Data Ram Size
128 KB
On-chip Adc
Yes
Operating Supply Voltage
1.71 V to 3.6 V
Operating Temperature Range
- 40 C to + 105 C
Package / Case
LQFP-80
Mounting Style
SMD/SMT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MK30DN512ZVLK10
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Modes of operation
27.2 Modes of operation
The FMC only operates when the device accesses the flash memory.
In terms of device power modes, the FMC only operates in run and wait modes, including
VLPR and VLPW modes.
For any device power mode where the flash memory cannot be accessed, the FMC is
disabled.
27.3 External signal description
The FMC has no external signals.
27.4
The programming model consists of the FMC control registers and the program visible
cache (data and tag/valid entries).
562
• Interface between the device and the dual-bank flash memory:
• For bank 0 and bank 1: Acceleration of data transfer from program flash memory to
the device:
• 8-bit, 16-bit, and 32-bit read operations to program flash memory.
• For bank 0 and bank 1: Read accesses to consecutive 32-bit spaces in memory
• Crossbar master access protection for setting no access, read only access, write
• 64-bit prefetch speculation buffer with controls for instruction/data access per
• 4-way, 8-set, 64-bit line size cache for a total of thirty-two 64-bit entries with
• Single-entry buffer with enable per bank
• Invalidation control for the speculation buffer and the single-entry buffer
Memory map and register descriptions
return the second read data with no wait states. The memory returns 64 bits via
the 32-bit bus access.
only access, or read/write access for each crossbar master.
master and bank
controls for replacement algorithm and lock per way for each bank
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Freescale Semiconductor, Inc.

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