MK30DN512ZVLK10 Freescale Semiconductor, MK30DN512ZVLK10 Datasheet - Page 526

• Manufacturer Part Number: MK30DN512ZVLK10
• Description: ARM Microcontrollers - MCU KINETIS 512K SLCD
• Manufacturer: Freescale Semiconductor

Specifications of MK30DN512ZVLK10

• Core: ARM Cortex M4
• Processor Series: K30
• Data Bus Width: 32 bit
• Maximum Clock Frequency: 50 MHz
• Program Memory Size: 512 KB
• Data Ram Size: 128 KB
• On-chip Adc: Yes
• Operating Supply Voltage: 1.71 V to 3.6 V
• Operating Temperature Range: - 40 C to + 105 C
• Package / Case: LQFP-80
• Mounting Style: SMD/SMT

Functional Description
526
FLL Engaged Internal
(FEI)
FLL Engaged External
(FEE)
FLL Bypassed Internal
(FBI)
Mode
FLL engaged internal (FEI) is the default mode of operation and is entered when all the following
condtions occur:
In FEI mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the 32
kHz Internal Reference Clock (IRC). The FLL loop will lock the DCO frequency to the FLL factor, as
selected by the C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency . Refer
to the C4[DMX32] bit description for more details. In FEI mode, the PLL is disabled in a low-power
state unless C5[PLLCLKEN] is set.
FLL engaged external (FEE) mode is entered when all the following conditions occur:
In FEE mode, MCGOUTCLK is derived from the FLL clock (DCOCLK) that is controlled by the
external reference clock. The FLL loop will lock the DCO frequency to the FLL factor, as selected
by C4[DRST_DRS] and C4[DMX32] bits, times the external reference frequency, as specified by
the C1[FRDIV] and C2[RANGE]. Refer to the C4[DMX32] bit description for more details. In FEE
mode, the PLL is disabled in a low-power state unless C5[PLLCLKEN] is set.
FLL bypassed internal (FBI) mode is entered when all the following conditions occur:
In FBI mode, the MCGOUTCLK is derived either from the slow (32 kHz IRC) or fast (2 MHz IRC)
internal reference clock, as selected by the C2[IRCS] bit. The FLL is operational but its output is not
used. This mode is useful to allow the FLL to acquire its target frequency while the MCGOUTCLK is
driven from the C2[IRCS] selected internal reference clock. The FLL clock (DCOCLK) is controlled
by the slow internal reference clock, and the DCO clock frequency locks to a multiplication factor,
as selected by the C4[DRST_DRS] and C4[DMX32] bits, times the internal reference frequency.
Refer to the C4[DMX32] bit description for more details. In FBI mode, the PLL is disabled in a low-
power state unless C5[PLLCLKEN] is set.
Description
• C1[CLKS] bits are written to 00
• C1[IREFS] bit is written to 1
• C6[PLLS] bit is written to 0
• C1[CLKS] bits are written to 00
• C1[IREFS] bit is written to 0
• C1[FRDIV] must be written to divide external reference clock to be within the range of 31.25
• C6[PLLS] bit is written to 0
• C1[CLKS] bits are written to 01
• C1[IREFS] bit is written to 1
• C6[PLLS] is written to 0
• C2[LP] is written to 0
kHz to 39.0625 kHz
K30 Sub-Family Reference Manual, Rev. 6, Nov 2011
Table 24-14. MCG Modes of Operation
Table continues on the next page...
Freescale Semiconductor, Inc.