M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 102

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.70. DMAC block diagram
Rev.2.00
REJ03B0005-0200
Direct memory access controller
This microcomputer has four DMAC (direct memory access controller) channels that allow data to be sent to memory
without using the CPU. DMAC shares the same data bus with the CPU. The DMAC is given a higher right of using the
bus than the CPU, which leads to working the cycle stealing method. On this account, the operation from the occurrence
of a DMA transfer request signal to the completion of 1-word (16-bit) or 1-byte (8-bit) data transfer can be performed at
high speed. Figure 1.70 shows the DMAC block diagram. Table 1.37 shows the DMAC specifications. Figure 1.71 to
Figure 1.73 show the registers used by the DMAC.
Either a write signal to the software DMA request bit or an interrupt request signal can be used as the DMA transfer
request signal. But the DMA transfer is not affected by either the interrupt enable flag (I flag) or by the interrupt priority
level. The DMA transfer doesn't affect any interrupts either.
If the DMAC is active (the DMA enable bit is set to 1), data transfer starts every time a DMA transfer request signal occurs.
If the cycle of the occurrences of DMA transfer request signals is higher than the DMA transfer cycle, there can be
instances in which the number of transfer requests doesn't match the number of transfers. For details, see the descrip-
tion of the DMA request bit.
Oct 16, 2006
Note: Pointer is incremented by a DMA request.
page 100 of 264
DMA0 transfer counter reload register TCR0 (16)
DMA0 transfer counter TCR0 (16)
DMA1 transfer counter reload register TCR1 (16)
DMA1 transfer counter TCR1 (16)
DMA2 transfer counter reload register TCR2 (16)
DMA2 transfer counter TCR2 (16)
DMA3 transfer counter reload register TCR3 (16)
DMA3 transfer counter TCR3 (16)
(addresses 0029
(addresses 0039
(addresses 0189
(addresses 0199
Data bus high-order bits
Data bus low-order bits
16
16
16
16
, 0028
, 0038
, 0188
, 0198
16
16
16
16
Address bus
)
)
)
)
DMA0 source pointer SAR0(20)
DMA0 destination pointer DAR0 (20)
DMA0 forward address pointer (20) (Note)
DMA1 source pointer SAR1 (20)
DMA1 destination pointer DAR1 (20)
DMA3 source pointer SAR3 (20)
DMA1 forward address pointer (20) (Note)
DMA2 source pointer SAR2(20)
DMA2 destination pointer DAR2 (20)
DMA2 forward address pointer (20) (Note)
DMA3 destination pointer DAR3 (20)
DMA3 forward address pointer (20) (Note)
DMA latch high-order bits
(addresses 0022
(addresses 0032
(addresses 0182
(addresses 0192
DMA latch low-order bits
(addresses 0026
(addresses 0036
(addresses 0186
(addresses 0196
16
16
16
16
to 0020
to 0030
to 0180
to 0190
16
16
16
16
16
16
16
16
to 0024
to 0034
to 0184
to 0194
)
)
)
)
16
16
16
16
)
)
)
)
DMA