M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 96

IC M16C/24 MCU FLSH 128K 100LQFP

M30245FCGP#U1

Manufacturer Part Number
M30245FCGP#U1
Description
IC M16C/24 MCU FLSH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/20r
Datasheet

Specifications of M30245FCGP#U1

Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SPI, SSI, UART/USART, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
82
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
R8C
Maximum Speed
16 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
82
Interface Type
USB/UART/I2C/SPI
On-chip Adc
8-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30245FCGP#U1M30245FCGP
Manufacturer:
RENESAS
Quantity:
102
Company:
Part Number:
M30245FCGP#U1
Manufacturer:
TDK-EPCOS
Quantity:
54 000
Company:
Part Number:
M30245FCGP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M30245 Group
Figure 1.61. USB Endpoint x OUT Control and Status register (EPxOCS)
Rev.2.00
REJ03B0005-0200
• OUTxCSR11 (ISO):
The CPU writes "1" to this bit to set the endpoint as an isochronous data transfer endpoint.
• OUTxCSR12 (SEND_STALL):
The CPU writes "1" to this bit when the endpoint is stalled (receiver halt). The USB FCU returns STALL handshakes
while this bit is set. The CPU writes "0" to clear this bit, if the STALL condition no longer exists.
• OUTxCSR13 (AUTO_CLR):
The CPU writes "1" to this bit to enable the AUTO_CLR function. AUTO_CLR takes place when a data packet (or a data
set, in continuous mode) is unloaded from the buffer, even if the data packet is less than MAXP (or data set is less than
BUF_SIZ, in continuous mode). See "OUT (Receive) FIFO" operation for details.
USB Endpoint x OUT Control and Status register
(b15)
0
b7
0
Oct 16, 2006
(b8)
page 94 of 264
b0
b7
b0
Note: Always read a "0" when writing to this bit
Bit Symbol
OUTxCSR0
OUTxCSR1
OUTxCSR2
OUTxCSR3
OUTxCSR4
OUTxCSR5
OUTxCSR6
OUTxCSR7
OUTxCSR8
OUTxCSR9
OUTxCSR10
OUTxCSR11
OUTxCSR12
OUTxCSR13
Reserved
Symbol
EPxOCS (x = 1 - 4)
OUT_BUF_STS0 flag
OUT_BUF_STS1 flag
OVER-RUN flag
FORCE_STALL flag
DATA_ERR flag
CLR_OUT_BUF_RDY
CLR_OVER_RUN
CLR_FORCE_STALL
CLR_DATA_ERR
TOGGLE_INIT
FLUSH
ISO
SEND_STALL
AUTO_CLR
Bit Name
02B6
02C6
Address
16
16
These two bits indicate the EPx OUT buffer status:
Bit1
0
0
1
1
0 : No over run detected
1 : Over run detected
0 : No packet size larger than MAXP violation detected
1 : Packet size larger than MAXP violation detected
0 : No data error detected
1 : Data error detected
0 : No action
1 : Data set unloaded from the OUT buffer (updates status flags)
0 : No action
1 : Clears OVER_RUN flag
0 : No action
1 : Clears FORCE_STALL flag
0 : No action
1 : Clears DATA_ERR flag
0 : No action
1 : Initialize the next data PID as a DATA0 for reception
0 : No action
1 : Flush out one data set
0 : Select non-isochronous endpoint
1 : Select isochronous endpoint
0 : No STALL by CPU
1 : STALL by CPU
0 : AUTO_CLR disabled
1 : AUTO_CLR enabled
Must always be set to "0"
, 02BE
, 02CE
16
16
Bit0
0 : No data set in the OUT buffer
1 : Single buffer mode: N/A
0 : Single buffer mode: N/A
1 : Single buffer mode: one data set in the OUT buffer
,
Double buffer mode: N/A
Double buffer mode: one data set in the OUT buffer
Double buffer mode: two data sets in the OUT buffer
Function
When reset
0000
16
Universal Serial Bus
O X
O X
O X
O X
R W
O X
O O
O O
O O
O O
O O
O O
O O
O O
O O
O O
Note
Note
Note
Note
Note
Note

Related parts for M30245FCGP#U1