M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 243

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Table 1.95. Memory expansion mode and microprocessor mode
Figure 1.199. Port P0 to P10 measurement circuit
Rev.2.00
REJ03B0005-0200
Note 1:Calculated according toothe BCLK frequency as shown below:
Note 2: Calculated as follows:
Note 3: Calculated as follows:
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
d (BCLK-HLDA)
d (BCLK-AD)
h (BCLK-AD)
h (RD-AD)
h (WR-AD)
d (BCLK-CS)
h (BCLK-CS)
d (BCLK-ALE)
h (BCLK-ALE)
d (BCLK-RD)
h (BCLK-RD)
d (BCLK-WR)
h (BCLK-WR)
d (BCLK-DB)
h (BCLK-DB)
d (DB-WR)
h (WR-DB)
h (WR-CS)
Switching characteristics (Vcc = 3.3V, Vss=0V, Topr =-20 C to 85 C unless otherwise stated)
Symbol
(When PM16 = 0)
(When PM16 = 1)
Oct 16, 2006
Write high to Chip select high time
Address output delay time
Address output hold time
Address output hold time
Address output hold time
Chip select output delay time
Chip select output hold time
ALE signal output delay time
ALE signal output hold time
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time
Data output tristate time
Data output delay time
Data output hold time
HLDA output delay time
t
t
d (DB-WR) = (m-0.5) X
d (DB-WR) = m X
page 241 of 264
t
t
h (WR-DB) =
h (WR-CS) =
Parameter
t
t
cyc / 2
cyc / 2
t
cyc - 40nS
t
cyc - 40nS
P10
P0
P1
P2
P3
P4
P5
P6
P7
P8
P9
}
30pF
0 Wait selected: m = 1
1 Wait selected: m = 1
2 Wait selected: m = 2
3 Wait selected: m = 3
See Figure 1.199
VIL = 0.2Vcc,
VIH = 0.8Vcc,
VOL = 0.5Vcc,
VOH = 0.5Vcc
Measuring
condition
Electrical Characteristics
(Note 1)
(Note 2)
(Note 3)
Min.
0
0
Standard
0
0
0
0
0
0
Max.
30
30
30
30
30
40
40
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns