M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 199

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
CPU Rewrite Mode
Overview
In CPU rewrite mode, the on-chip flash memory can be read, programmed, or erased under control of the Central
Processing Unit (CPU). Only the user ROM area, shown in Figure 1.149, can be rewritten. The boot of the user ROM
area.ROM area cannot be rewritten. Make sure the program and block erase commands are issued only for each block
The control program for CPU rewrite mode can be stored in either the user ROM or the boot ROM area. Because the
flash memory cannot be read from the CPU, the rewrite control program must be transferred to an area other than
the internal flash memory before it can be executed.
In the CPU rewrite mode, the CPU erases, programs and reads the internal flash memory as instructed by software
commands. Operations are executed from a memory other than the internal flash memory, such as the internal RAM.
When the CPU rewrite mode select bit (bit 1 at address 02F7
software commands can be accepted. Read and write software commands and data to even-numbered addresses ("0"
for address A
Commands are ignored with odd-numbered addresses. Use software commands to control program and erase operations.
The status register can verify if a program or erase operation has terminated normally or in error.
Figure 1.150 shows the flash memory control register 0. Figure 1.151 shows a flowchart for enabling/disabling the
CPU rewrite mode. Always follow the operation as indicated in these flowcharts.
Bit 0 is the RY/BY status flag used exclusively to read the operating status of the flash memory. During programming
and erase operations, it is "0". Otherwise, it is "1".
Bit 1 is the CPU rewrite mode select bit. The CPU rewrite mode is entered by setting this bit to "1" to make software
commands accepted. In CPU rewrite mode, the CPU becomes unable to access the internal flash memory directly
so, write bit 1 in an area other than the internal flash memory. To set this bit to "1", it is necessary to write "0" and then
write "1" in succession when the NMI pin is "H" level. The bit can be set to "0" by only writing "0".
Bit 2 is the lock bit disable bit. By setting this bit to "1", it is possible to disable erase and write protect (block lock)
effected by the lock bit data. The lock bit disable select bit only disables the lock bit function; it does not change the
lock data bit value. However, if an erase operation is performed when this bit = "1", the lock bit data that is "0" (locked) is
set to "1" (unlocked) after being erased. To set this bit to "1", it is necessary to write "0" and then write "1" in succession.
This bit can be controlled only when the CPU rewrite mode select bit = "1".
Bit 3 is the flash memory reset bit used to reset the control circuit of the internal flash memory. This bit is used when
exiting CPU rewrite mode and when flash memory access has failed. When the CPU rewrite mode select bit is "1",
writing "1" to this bit resets the control circuit. To release the reset, set this bit to "0".
Bit 5 is the user ROM area select bit that is effective only in boot mode. If this bit is set to "1", the accessed area is switched from
the boot ROM area to the user ROM area. When the CPU rewrite mode is used in boot mode, set this bit to "1". If the
microcomputer is booted from the user ROM area, the user ROM area is always accessed and this bit has no effect.
When in boot mode, the function of this bit is effective regardless of whether the CPU rewrite mode is on or off. Use a
control program that is not running in the internal flash memory to rewrite this bit.
Oct 16, 2006
0
) in 16-bit units. For 8-bit mode, always write 8-bit software commands to even-numbered addresses.
page 197 of 264
16
) is set to "1", transition to CPU rewrite mode occurs and
CPU Rewrite Mode