M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 254

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.207. Setting routine of DMA control registers
Rev.2.00
REJ03B0005-0200
DMA
(1) Additional description of the DMA enable bit
(2) Additional description of the DMA request bit
Bit 3 of the DMA0 and DMA1 control registers is assigned as the DMA enable bit. Setting the DMA enable bit to “1”
makes DMA active. If data transfer starts immediately after the DMA becomes active, the DMAC performs the
following operations.
Thus, writing “1” to the DMA enable bit when DMA is active causes the above operations to be carried out, and the
DMAC operates again from the initial state at that point.
Bit 2 of the DMA0 and DMA1 control registers is assigned as the DMA request bit. The DMA request bit is set to “1” if
a DMA transfer request signal occurs even if DMA is not active. Also, changing the DMA transfer request cause
select bits may set the DMA request bit to “1”. Make sure to set the DMA request bit to “0” after changing the DMA
request cause select bits.
The DMA request bit is set to “1” if a DMA transfer request signal occurs and is set to “0” immediately after data
transfer starts. If DMA is active, data transfer starts immediately, so the value of the DMA request bit, if read by
software, will be “0” in most cases. To determine whether DMA is active, read the DMA enable bit. Figure 1.207
shows the setting routine for the DMA-related registers.
(a) The value of either the source pointer or the destination pointer, whichever is set to the forward direction, is
(b) The value of the transfer counter register is reloaded to the transfer counter.
Oct 16, 2006
reloaded to the forward direction address pointer.
page 252 of 264
No
Select DMA request causes
Set DMA control register
Set destination pointer
DMA request bit ← "0"
DMA request bit ← "1"
DMA enable bit = "0"?
Set transfer counter
Set source pointer
START
END
Yes
Usage Notes