M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 133

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.93. Serial I/O-related registers (5)
Rev.2.00
REJ03B0005-0200
Oct 16, 2006
UARTi special mode register 4 (i= 0 to 3)
b7
UARTi special mode register 3 (i= 0 to 3)
b6
b7
b6
b5
b5
b4
b3
b4
page 131 of 264
b2
b3
b2
b1
b0
b1
b0
Note 1: These bits automatically become "0" when a start condition is generated.
Note 2: This bit is unavailable when SCLi is external clock.
Bit Symbol
STAREQ
RSTAREQ
STPREQ
STSPSEL
ACKD
ACKC
SCLHI
SWC9
Note 1: Set SS function after setting CTS/RTS disable bit (bit 4 of UARTi transfer/receive control register 0)
Note 2: Only "0" may be written.
Note 3: These bits are used for SDAi (TxDi) output digital delay when using UARTi for I
Note 4: The amount of delay varies with the load on SCLi and SDAi pins. Also, when external clock
Bit Symbol
Symbol
UiSMR4 (i = 0 to 3)
SSE
CKPH
DINC
NODC
ERR
DL0
DL1
DL2
Symbol
UiSMR3 (i = 0 to 3)
Otherwise, set these to "000".
to "1".
is selected, delay is increased by approximately 100ns.
Start condition generate
bit (Note 1)
Restart condition
generate bit (Note 1)
Stop condition generate bit
(Note 1)
SCL, SDA output select bit
ACK data bit
ACK data output enable bit
SCL output stop enable bit
SCL waitt output bit 3
SS port function enable bit
(Note 1)
Clock phase set bit
Serial input port set bit
Clock output select bit
Fault error flag
SDA (TxDi) digital delay
time set bit (Notes 3,4)
Bit Name
Bit Name
03A4
(Note 2)
03A5
16
, 0364
16
, 0365
Address
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Clear
1 : Start
0 : Ordinal block
1 : Start/stop condition generate block
0 : ACK
1 : NACK
0 : SI /O data output
1 : ACKD output
0 : Disabled
1 : Enabled
0 : SCL "L" hold disabled
1 : SCL "L" hold enabled
16
, 0334
b7 b6 b5
Address
0 : SS function disabled
1 : SS function enabled
0 : No clock delay
1 : Clock delay
0 : Select TxDi and RxDi (master mode)
1 : Select STxDi and SRxDi (slave mode)
0 : CLKi is CMOS output
1 : CLKi is N-channel open drain output
0 : No fault error
1 : Fault error (Note 2)
0 0 0 : No delay
0 0 1 : 1 to 2-cycle of UiBRG count source
0 1 0 : 2 to 3-cycle of UiBRG count source
0 1 1 : 3 to 4-cycle of UiBRG count source
1 0 0 : 4 to 5-cycle of UiBRG count source
1 0 1 : 5 to 6-cycle of UiBRG count source
1 1 0 : 6 to 7-cycle of UiBRG count source
1 1 1 : 7 to 8-cycle of UiBRG count source
16
, 0335
16
, 0324
16
, 0325
16
Function
16
Function
When reset
00
When reset
Serial Communication
16
2
00
C interface.
16
O
R W
O
O
O
O
O
O
O
R W
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O