M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 69

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Clearing the Interrupt request bit
Even when the IR bit (bit 3 of the interrupt control register) is cleared to "0" (interrupt not requested), it may not actually
get cleared to "0" depending on the instruction used to clear it. Therefore, use the MOV instruction to clear the IR bit.
Rewriting the interrupt control register
Rewrite the interrupt control register so that it does not generate an interrupt request for that register. If an interrupt
request occurs, rewrite the interrupt control register after the interrupt is disabled. Some program examples are de-
scribed below.
When an instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the interrupt request
bit is not always set even if the interrupt request for that register has been generated. This will depend on the instruction.
If this creates problems, use the instructions below to change the register.
Instructions: AND, OR, BCLR, BSET
Examples 1 through 3 show how to prevent the I flag from being set to "1" (interrupts enabled) before the interrupt control
register is rewritting, due to the effects of the internal bus and the instruction queue buffer.
The reason why two NOP instructions (four using the HOLD function) or a dummy read is inserted before "FSET I " in
Examples 1 and 2, is to prevent the interrupt enable flag I from being set before the interrupt control register is
rewritten due to the effects of the instruction queue.
Example 1:
Example 2:
Example 3:
Oct 16, 2006
INT_SWITCH1:
INT_SWITCH2:
INT_SWITCH3:
page 67 of 264
FCLR
AND.B
NOP
NOP
FSET
FCLR
AND.B
MOV.W
FSET
PUSHC
FCLR
AND.B
POPC
I
#00h, 0054h
I
I
#00h, 0054h
MEM, R0
I
FLG
I
#00h, 0054h
FLG
:Disable interrupts.
;Clear TA0IC int. priority level and int. request bit.
;Four NOP instructions are required when using the HOLD function.
;Enable interrupts.
:Disable interrupts.
;Clear TA0IC int. priority level and int. request bit.
;Dummy read.
;Enable interrupts.
;Push Flag register onto stack
;Diable interrupts.
;Clear TA0IC int. priority level and int. request bit.‘
;Enable interrupts.
Interrupts