M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 89

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
USB Endpoint 0 CSR
The Endpoint 0 CSR (Control & Status register), shown in Figure 1.55, contains the control and status information
for EP0.
• EP0CSR0 (OUT_BUF_RDY):
A status flag, "1" indicates a SETUP packet or an OUT data set is in the OUT buffer, ready for the CPU to unload.
During the data phase, if noncontinuous mode is set, the OUT_BUF_RDY bit is "1" when:
• A data packet is received from the host
During the data phase, if continuous mode is set, the OUT_BUF_RDY bit is "1" when:
• A data set equal to 128 bytes is received from the host
• A short packet is received from the host
• A control write status phase has started with pending OUT data packets in the buffer.
• EP0CSR1 (IN_BUF_RDY):
A status flag, "1" indicates a data set is in the IN buffer, ready for transmission. The USB FCU clears this bit after the data
set is successfully transmitted to the host, or the EP0CSR5 (SETUP_END) bit is set.
• EP0CSR2 (SETUP):
A status flag, "1" indicates a SETUP packet has been received. The SETUP Flag is a subset of the OUT_BUF_RDY flag.
• EP0CSR3 (DATA_END):
A status flag, "1" indicates the CPU sets the DATA_END bit. The USB FCU clears this flag after the status phase has
started or a new SETUP is received. This flag is a maskable flag. If DATA_END Flag Mask is a "1" (default), this
DATA_END flag is always a "0" and no EP0 interrupt is caused by the DATA_END flag being cleared.
• EP0CSR4 (FORCE_STALL):
A status flag, "1" indicates a protocol error when one of the following occurs:
• Host sends an IN token in the absence of a SETUP stage
• Host sends a bad data toggle in the STATUS stage, (i.e. DATA0 is used)
• Host sends a bad data toggle in the SETUP stage, (i.e. DATA1 is used)
• Host requests more data than specified in the SETUP state, (i.e. IN token comes after DATA_END bit is set)
• Host sends more data than specified in the SETUP state, (i.e. OUT token comes after DATA_END bit is set)
• Host sends a larger data packet than the MAXP size
All of the conditions stated (except bad data toggle in the SETUP stage) cause the device to send a STALL handshake
for the current IN/OUT transaction. For the bad data toggle in the SETUP stage, the device sends ACK for the SETUP
stage and then sends STALL for the next IN/OUT transaction. A STALL handshake caused by the above conditions lasts
for one transaction and terminates the ongoing control transfer. Any packet after the STALL handshake will be seen as
the beginning of a new control transfer.
Oct 16, 2006
page 87 of 264
Universal Serial Bus