M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 154

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.111. Transmit/receive timing in master mode (Internal clock)
Rev.2.00
REJ03B0005-0200
Clock phase setting
With bit 1 of UARTi special mode register 3 and bit 6 of UARTi transmit/receive control register 0, four combinations of
transfer clock phase and polarity can be selected. Bit 6 of UARTi transmit/receive control register 0 sets transfer clock
polarity, whereas bit 1 of UiSMR3 register sets transfer clock phase. Transfer clock phase and polarity must be the
same between the master and slave involved in the transfer.
• Master (Internal clock) (DINC=0)
Figure 1.111 shows the transmit and receive timing.
• Slave (External clock) (DINC=1)
When "0" for CKPH bit (bit 1 of UiSMR3) is selected and SSi input pin is "H" level, output data is high impedance.
When an SSi input pin is "L" level, the serial transmission start condition is satisfied even though output is indeterminate
and serial transmission is synchronized with the clock. Figure 1.112 shows the timing.
When "1" is selected for CLPH bit and SSi input pin is "H" level, output data is high impedance. When an SSi input
pin is "L" level, the first data is output and serial transmission is synchronized with the clock. Figure 1.113 shows the
timing.
Oct 16, 2006
Clock output
(CKPOL=0, CKPH=0)
Clock output
(CKPOL=1, CKPH=0)
Data output timing
Data input timing
Clock output
(CKPOL=1, CKPH=1)
Clock output
(CKPOL=0, CKPH=1)
Master SS input
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"L"
"H"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
"H"
"L"
D
0
D
1
D
2
D
Serial Interface Special Function (SPI mode)
3
D
D
4
4
D
5
D
6
D
7