M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 35

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Oscillation
R/W signal, address bus, data bus, CS, BHE
Programmable I/O ports
HLDA
Internal peripheral circuits
ALE signal
Address bus
Data
RD, WR, WRL, WRH
BHE
CS
ALE
Table 1.20. Microcomputer status in HOLD state
Table 1.21. External bus status when the internal area is accessed
Oct 16, 2006
HOLD signal
External bus status when the internal area is accessed
BCLK output
Item
___________
The hold signal is used to transfer the bus privileges from the CPU to the external circuits. Inputting "L" to the
HOLD pin places the microcomputer in the hold state at the end of the current bus access. This status is
maintained and "L" is output from the HLDA pin as long as "L" is input to the HOLD pin. Table 1.20 shows the
microcomputer status in the hold state.
Bus priorities listed in descending order are: HOLD, DMAC, and CPU.
Table 1.21 shows the external bus status when the internal area is accessed.
The user can choose to output BCLK on P5
set to "1", the output is left floating.
Note: Before attempting to change the contents of the processor mode register 0, set bit 1 of the protect register
(address 000A
When read
When write
page 33 of 264
Item
16
) to "1".
P0, P1, P2, P3, P4, P5
P6, P7, P8, P9, P10
Address output
Floating
Output data
RD, WR, WRL, WRH output
BHE output
Output "H"
Output "L"
SFR acc ess ed
__________
3
by use of bit 7 of processor mode register 0 (0004
___________
On
Floating
Floating
Maintains status when hold signal is received
Output "L"
On (Watchdog timer is stopped)
Undefined
Maintain status before accessing address of external
area
Floating
Undefined
Output "H"
Maintain status before accessing status of external
area
Output "H"
Output "L"
Internal ROM/RAM acce sse d
Status
___________
Processor Mode
16
) (Note). When