M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 207

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Precautions
Operation speed
During CPU rewrite mode, set the main clock frequency to 6.25MHz or less using the main clock division select bits (bit
6 at address 0006
Prohibited Instructions
The UND, INTO, JMPS, JSRS, and BRK instructions cannot be used during CPU rewrite mode because they refer to the
internal data of the flash memory.
Prohibited Interrupts
The address match interrupt cannot be used during CPU rewrite mode because it refers to the internal data of the flash
memory. If the interrupt's vector is in the variable vector table, it can be used by transferring the vector into the RAM area.
The NMI and watchdog timer interrupts can be used to change the CPU rewrite mode select bit forcibly to normal mode
(FMR01="0") when the interrupt occurs. If the rewrite operation is stopped when the NMI or watchdog timer interrupts
occurs, the CPU rewrite mode select bit should be set to "1" and the erase/program operation should be repeated.
Reset
Reset input is always accepted.
Access
To set the CPU rewrite mode select bit, and the lock bit disable bit to "1", the user must write a "0" and then a "1". This
sequence must be followed to set this bit to "1". This is necessary to ensure that no interrupt or DMA transfer will be
executed during the interval.
Write to the CPU rewrite mode select bit when NMI pin is a "H" level.
Access disable
Write the CPU rewrite mode select bit, and the user ROM area select bit in an area other than the internal flash memory.
Writing in the user ROM area
If power is lost while rewriting blocks that contain the flash rewrite program with the CPU rewrite mode, the blocks may
not be correctly rewritten. Afterwards, it is possible that the flash memory can not be rewritten. Therefore, use the
standard serial I/O mode or parallel I/O mode to rewrite these blocks.
Using the lock bit
In CPU rewrite mode, use a program that can set and clear the lock bit disable bit (FMR02).
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and bits 6 and 7 at address 0007
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16
).
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CPU Rewrite Mode