M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 87

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.52. USB ISO Control register (USBISOC)
Rev.2.00
REJ03B0005-0200
USB ISO Control Register
The USB ISO Control Register, shown in Figure 1.52, contains the isochronous data transfer control and status
information.
• ISO_UPD
The ISO_UPD bit is a global bit for endpoints 1-4 and works with IN isochronous pipes only.
When ISO_UPD = "0", a data packet in an endpoints IN buffer is always 'ready to transmit' when it receives the next IN
token from the host (with matched address and endpoint number), if the CPU writes "1" to the corresponding endpoint's
SET_IN_BUF_RDY bit, or in AUTO_SET case, a data packet equal to EPx's MAXP value has been written to the FIFO.
When ISO_UPD = "1" and the ISO bit of the corresponding endpoint's IN CSR is set, the internal 'ready to transmit' signal
to the transmit control logic is not activated when the CPU writes "1" to the corresponding endpoint's SET_IN_BUF_RDY
bit, or in the AUTO_SET case, a data packet equal to EPx's MAXP value has been written to the FIFO. Instead it is
activated when the next SOF is received, thus the data loaded in frame n is transmitted out in frame n+1.
• AUTO_FL
When AUTO_FL = "1", ISO_UPD = "1", IN endpoint's ISO bit is set, and the IN endpoint's IN_BUF_STS1 & IN_BUF_STS0
are "1"s at the time the USB FCU detects a SOF (from the host or from artificial SOF), it automatically flushes the oldest
packet from the IN buffer. In this case, IN_BUF_STS1 & IN_BUF_STS0 are "1"s and indicate that two data packets are
in the IN buffer. Double buffering is required for ISO transfer.
• ART_SOF_ENA
An artificial SOF function enable bit.
• ART_SOF_SET
Artificial SOF function status flag. When this flag is "1", it indicates that an artificial SOF will be generated by the device
because of a missing or corrupt SOF packet (when the SOF enable bit is set to "1"). A corrupt SOF packet is any SOF
having an error in its 8-bit Pakcet ID (PID) field.
• CLR_ART_SOF
The CPU writes "1" to this bit to clear the ART_SOF_SET flag.
Oct 16, 2006
USB ISO Control register
(b15)
0
b7
0 0 0 0 0 0 0 0
page 85 of 264
(b8)
b0
b7
0 0
b0
AUTO_FL
ISO_UPD
ART_SOF_ENA
ART_SOF_SET
CLR_ART_SOF
Reserved
Note 1: Read only
Note 2: Always read "0"
Bit Symbol
Symbol
USBISOC
Auto flush
ISO Update
Artificial SOF enable
Artificial SOF set flag
Clear artificial SOF set flag
Bit Name
Address
028C
16
0 : Hardware auto flush disabled
1 : Hardware auto flush enabled
0 : ISO update disabled
1 : ISO update enabled
0 : Artificial SOF disabled
1 : Artificial SOF enabled
0 : Not generated by device (Note 1)
1 : Generated by the device
0 : No action (Note 2)
1 : Clear ART_SOF_SET flag
Must always be set to "0"
Function
When reset
0000
Universal Serial Bus
16
O O
O O
R W
O O
O O
O O
O X