M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 79

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
EP1-4 OUT (Receive) FIFOs
AUTO_CLR and continuous transfer mode are disabled:
AUTO_CLR is disabled and continuous transfer mode enabled:
Single Buffer Mode:
Double Buffer Mode:
Single Buffer Mode:
Double Buffer Mode:
The CPU reads data from the endpoint’s FIFO Data Register. The read pointer automatically increments by 2 in word
accessing mode or by 1 in byte accessing mode after a read. The CPU must only read data from the FIFO Data Register
when the OUT_BUF_STS1 flag of the corresponding EPx OUT CSR is a "1".
The user can program each OUT endpoint’s buffer size and starting location, and assign a buffer size up to 1024
bytes in units of 64 bytes to an endpoint. If double buffer mode is selected, the effective buffer size is 2 x buffer size
specified.
Continuous transfer mode is available for OUT EP1-4 bulk transfers only. When the continuous transfer mode is enabled,
the user is responsible for ensuring that the buffer size is a multiple of the MAXP value. Also, the user must ensure
that the last data set from the host either contains a short packet or is equal to the buffer size, otherwise there is no
interrupt or status that will signify that the last data set was received.
AUTO_CLR function is available for OUT EP1-4.
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags from 00
after it has successfully received a data packet from the host.
The CPU writes "1" to the CLR_OUT_BUF_RDY bit after the data packet has been unloaded from the buffer by the CPU
(updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 11
The USB FCU updates the corresponding EPx OUT CSR's OUT_BUF_STS1 & OUT_BUF_STS0 flags after it has
successfully received a data packet from the host.
• If the buffer has only one data packet, the buffer status flags transition from 00
• If the buffer has two data packets, the buffer status flags transition from 10
The CPU writes "1" to the CLR_OUT_BUF_RDY bit after a data packet has been unloaded from the buffer by the
CPU (updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags).
• If the buffer has one more data packet in it, the buffer status flags transition from 11
• If the buffer has no more data packet in it, the buffer status flags transition from 10
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags from 00
11
The CPU writes "1" to the CLR_OUT_BUF_RDY bit after the data set has been unloaded from the buffer by the CPU
(updates the OUT_BUF_STS1 & OUT_BUF_STS0 flags from 11
The USB FCU updates the corresponding EPx OUT CSR’s OUT_BUF_STS1 & OUT_BUF_STS0 flags after it has
successfully received a data set equal to its buffer size or a short packet from the host..
• If the buffer has only one data set, the buffer status flags transition from 00
• If the buffer has two data sets, the buffer status flags transition from 10
2
after it has successfully received from the host a data set equal to the buffer size, or a short packet.
Oct 16, 2006
page 77 of 264
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