M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 59

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.33. Interrupt response time
Table 1.30. Time required for executing the interrupt sequence
Note 1: Add 2 cycles for DBC interrupt.
Note 2: Locate an interrupt vector address in an even address if possible.
Rev.2.00
REJ03B0005-0200
Interrupt vector address
Interrupt Response Time
'interrupt response time' is the period between when an interrupt occurs and when the first instruction within the
interrupt routine has been executed. This time comprises the period from the occurrence of an interrupt to the comple-
tion of the instruction under execution at that moment (a) and the time required for executing the interrupt sequence (b).
Figure 1.33 shows the interrupt response time.
Time (a) is dependent on the instruction under execution. Thirty cycles is the maximum required for the DIVX instruction
(without wait).
Time (b) is as shown in Table 1.30 . Figure 1.34 shows the time required for executing the interrupt sequence.
Add 1 cycle for either an address match interrupt or a single-chip interrupt.
Odd (Note 2)
Odd (Note 2)
Oct 16, 2006
Even
Even
Interrupt request generated
(a) Time from interrupt request is generated to when the instruction then under execution is completed.
(b) Time in which the instruction sequence is executed.
page 57 of 264
Instruction
Stack pointer (SP) value
(a)
Interrupt response time
Even
Even
Odd
Odd
Interrupt request acknowledged
Interrupt sequence
16-bit bus, without wait
(b)
18 cycles (Note 1)
19 cycles (Note 1)
19 cycles (Note 1)
20 cycles (Note 1)
interrupt routine
Instruction in
8-bit bus, without wait
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
20 cycles (Note 1)
Interrupts
Time