M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 90

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
• EP0CSR5 (SETUP_END):
A status flag, "1" indicates a premature completion of a control transfer when one of the following events occurs:
• A control transfer ends before the specific length of data is transferred during the data phase (status phase starts
before DATA_END bit is set)
• A new SETUP is received before successfully completing the status phase of the previous control transfer.
• EP0CSR6 (CLR_OUT_BUF_RDY):
The CPU writes a "1" to this bit after unloading a data set from the buffer. Writing a "1" to this bit clears the
OUT_BUF_RDY status flag.
• EP0CSR7 (SET_IN_BUF_RDY):
The CPU writes a "1" to this bit after loading a data set to the buffer. Writing a "1" to this bit sets the IN_BUF_RDY status
flag.
• EP0CSR8 (CLR_SETUP):
The CPU writes a "1" to this bit to clear the SETUP status flag.
• EP0CSR9 (SET_DATA_END):
The CPU writes a "1" to this bit when it writes (IN data phase) the last data packet to the buffer or reads (OUT data phase)
the last data packet from the buffer. The CPU sets this bit at the same time (using the same instruction) as it sets the
CLR_OUT_BUF_RDY bit or sets the SET_IN_BUF_RDY bit for the last data set. Writing a "1" to this bit sets the
DATA_END status flag.
• EP0CSR10 (CLR_FORCE_STALL):
The CPU writes a "1" to this bit to clear the FORCE_STALL status flag.
• EP0CSR11 (CLR_SETUP_END):
The CPU writes a "1" to this bit to clear the SETUP_END status flag.
• EP0CSR12 (SEND_STALL):
The CPU writes a "1" to this bit when it decodes an invalid or unsupported request from the host. The CPU should only
write a "1" to this bit at the same time it writes a "1" to EP0CSR6 (CLR_OUT_BUF_RDY). When this bit is a "1", the USB
FCU returns STALL handshakes for all subsequent IN/OUT transactions. The CPU writes a "0" to clear it after it receives
a new SETUP packet. It is up to the firmware to decide what SETUP packet should lead the clearing of the SEND_STALL
bit.
• EP0CSR13 (DATA_END_MASK):
This bit is for the CPU to mask or unmask the clearing of DATA_END as an EP0 interrupt source - default is masked
(clearing of DATA_END does not cause an EP0 interrupt).
Oct 16, 2006
page 88 of 264
Universal Serial Bus