M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 110

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.75. Example of the transfer cycles for a source read
Rev.2.00
REJ03B0005-0200
Oct 16, 2006
(1) 8-bit transfers
(2) 16-bit transfers and the source address is odd
(3) One wait is inserted into the source read under the conditions in (1)
(4) One wait is inserted into the source read under the conditions in (2)
BCLK
Address
bus
WR
Data
bus
BCLK
Address
bus
RD
WR
Data
bus
BCLK
Address
bus
RD
WR
Data
bus
BCLK
Address
bus
RD
WR
Data
bus
RD
Transferring 16-bit data on an 8-bit data bus (In this case, there are two destination write cycles)
(When 16-bit data is transferred on an 8-bit data bus, there are two destination write cycles)
16-bit transfers from even address and the source address is even.
Note : The same timing changes occur with the respective conditions at the destination as at the source.
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CPU use
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Source
Source
Source
Source
Source
Source
Destination
Source + 1
Source
Source
Destination
Source + 1
Destination
Destination
Dummy
cycle
Destination
Destination
Source + 1
Dummy
cycle
Source + 1
Dummy
cycle
Dummy
cycle
Dummy
cycle
Dummy
cycle
Destination
Destination
CPU use
CPU use
Dummy
cycle
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Dummy
cycle
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DMA