M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 33

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Memory
expansion mode
Microprocessor
mode
16-bit (BYTE = "L")
Data bus wid th
Data bus wid th
Table 1.16. External areas specified by the chip select signals
Table 1.17. Operation of RD, WRL, and WRH signals
Table 1.18. Operation of RD, WR, and BHE signals
(BYTE = “H”)
(BYTE = “L”)
Process or
mode
16-bit
8-bit
Oct 16, 2006
Read/write signals
With a 16-bit data bus (BYTE pin ="L"), bit 2 of the processor mode register 0 (address 0004
combinations of RD, BHE, and WR signals or RD, WRL, and WRH signals. With an 8-bit data bus (BYTE pin =
"H"), use the combination of RD, WR, and BHE signals. (Set bit 2 of the processor mode register 0 (address
0004
After a reset, the combination of RD, WRR, and BHE signals is automatically selected.
When switching to the RD, WRL, and WRH combination, do not write to external memory until bit 2 of the
processor mode register 0 (address 0004
processor mode register 0, set bit 1 of the protect register (address 000A
16
) to "0".) Tables 1.17 and 1.18 show the operation of these signals.
30000
(640 Kbytes)
30000
(832 Kbytes)
RD
page 31 of 264
H
H
H
H
L
L
L
L
_____
_____
RD
16
16
_____
H
H
H
L
CS0
to CFFFF
to FFFFF
______
________
_______
WRL
_____
H
H
H
H
L
L
L
L
16
16
_______
________
WRL
_____
_________
H
H
L
L
______
Not used
Not used
_____
______
28000
(32 Kbytes)
BHE
H
H
L
L
L
L
______
________
16
16
CS1
to 2FFFF
WRH
_______
) has been set . Before attempting to change the contents of the
H
H
L
L
Chip -select si gnal
_____
H/L
H/L
A0
H
H
L
L
L
L
_______
________
16
Read data
Write 1 byte of data to even address
Write 1 byte of data to odd address
Write data to both even and odd addresses
Write 1 byte of data to odd address
Read 1 byte of data from odd address
Write 1 byte of data to even address
Read 1 byte of data from even address
Write data from both even and odd addresses
Read data from both even and odd addresses
Write 1 byte of data
Read 1 byte of data
08000
(128 Kbytes)
________
16
External data bus status
CS2
External data bus status
to 27FFF
16
) to "1".
16
04000
(16 Kbytes)
16
Processor Mode
CS3
to 07FFF
16
) selects the
16