M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 136

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.94. Typical transmit/receive timing in clock synchronous serial I/O mode
Rev.2.00
REJ03B0005-0200
Oct 16, 2006
Over run error
flag (OER)
Receive interrupt
request bit (IR)
Transfer clock
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
CTSi
CLKi
TxDi
Transmit
register empty
flag (TXEPT)
Transmit interrupt
request bit (IR)
Receive enable
bit (RE)
Transmit enable
bit (TE)
Transmit buffer
empty flag (Tl)
RTSi
CLKi
RxDi
Receive complete
flag (Rl)
Example of receive timing when external clock is selected
Example of transmit timing when internal clock is selected
Shown in ( ) are bit symbols.
Shown in ( ) are bit symbols.
The above timing applies to the following settings:
The above timing applies to the following settings:
f
EXT
• Internal clock is selected.
• CTS function is selected.
• CLK polarity select bit = "0".
• Transmit interrupt cause select bit = "0".
• External clock is selected.
• RTS function is selected.
• CLK polarity select bit = "0".
: frequency of external clock
"H"
"L"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"H"
"1"
"0"
"1"
"0"
"L"
"1"
"0"
"1"
"0"
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Transferred from UARTi receive register
Data is set in UARTi transmit buffer register
D
to UARTi receive buffer register
0
D
0
D
1
D
1
T
D
Dummy data is set in UARTi transmit buffer register
CLK
2
D
2
D
3
Transferred from UARTi transmit buffer register to UARTi transmit register
D
3
D
Cleared to "0" when interrupt request is accepted, or cleared by software
Tc
4
D
4
D
1 / f
Receive data is taken in
5
Cleared to "0" when interrupt request is accepted, or cleared by software
D
5
D
EXT
6
D
6
D
7
Transferred from UARTi transmit buffer register to UARTi transmit register
D
Stopped pulsing because CTS = "H"
7
D
0
Tc = TCLK = 2(m + 1) / fi
The following conditions are met when the CLKi
input before data reception = "H"
D
0
Read out from UARTi receive buffer register
• Transmit enable bit
• Receive enable bit
• Dummy data write to UARTi transmit buffer register
D
Even if the reception is completed, RTS does not change. RTS
becomes "L" when the RI bit changes from "1" to "0".
1
D
fi : frequency of BRGi count source (f
m : value set to BRGi
1
D
2
D
2
D
3
D
3
D
4
D
4
D
5
D
5
D
6
D
"1"
"1"
D
6
7
Clock synchronous serial I/O mode
D
7
Stopped pulsing because transfer enable bit = "0"
D
D
0
0
D
D
1
1
, f
1
D
8
D
, f
2
2
32
D
D
3
)
3
D
D
4
4
D
D
5
5
D
D
6
6
D
7