M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 152

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Table 1.52. Functions changed by SCL, SDA output select bit
Figure 1.109. Functions changed by SCL, SDA output select bit
Rev.2.00
REJ03B0005-0200
SCL, SDA output
Start/stop condition interrupt factor
UARTi Special Mode Register 4 (UiSMR4)
Bit 0 is the start condition generate bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "1" and this bit is "1", the
start condition is generated.
Bit 1 is the restart condition generate bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "1" and this bit is "1",
the restart condition is generated.
Bit 2 is the stop condition generate bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "1" and this bit is "1", the
stop condition is generated.
Bit 3 is SCL, SDA output select bit. Table 1.52 shows the functions that are changed by this bit. Figure 1.109 shows the
functions changed by SCL, SDA output select bit.
Bit 4 is ACK data bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "0" and the ACK data output enable bit (bit
5 of UiSMR4) is "1", the content of ACK data bit is output to SDAi pin.
Bit 5 is ACK data output enable bit. When the SCL, SDA output select bit (bit 3 of UiSMR4) is "0" and this bit is "1", the
content of ACK data bit is output to SDAi pin.
Bit 6 is SCL output stop bit. When this bit is "1", SCLi output is stopped at stop condition detection. (High-Z status).
Bit 7 is SCL wait output bit 3. When this bit is "1", SCLi output is fixed to "L" at the falling edge of the 10th clock bit. When
this bit is "0", SCLi output fixed to "L" is released. This bit is unavailable when SCLi is external clock.
Master mode (CKDIR = 0, STSPSEL = 1)
SCL
SDA
STSPSEL = 0
Oct 16, 2006
STAREQ =1
Function
detection interrupt
Start condition
STSPSEL = 1
page 150 of 264
Output of S I/O control circuit
Start/stop condition detection
STSPSEL=0
STSPSEL = 0
Output of start/stop condition control
circuit
Completion of start/stop condition
generation
STPREQ = 1
STSPSEL=1
I
2
C Bus interface mode
STSPSEL = 1
Stop condition
detection interrupt
STSPSEL = 0