M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 157

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.114. Bus collision Detect Function-Related Bits
Rev.2.00
REJ03B0005-0200
Transfer clock
TxDi
RxDi
Timer Aj
Transfer clock
TxDi
RxDi
Bus collision
detect interrupt
request bit
UiC1 register
TE bit
Transfer clock
TxDi
CLKi
TxDi
RxDi
(1) UiSMR register ABSCS bit (bus collision detect sampling clock select)
(2) UiSMR register ACSE bit (auto clear of transmit enable bit)
(
3) UiSMR register SSS bit (Transmit start condition select)
If ABSCS=0, bus collision is determined at the rising edge of the transfer clock
Timer Aj : timer A3 when UART0; timer A4 when UART1; timer A0 when UART2; timer A3 when UART3)
If SSS bit=0, the serial I/O starts sending data one transfer clock cycle after the transmission enable condition is met.
If SSS bit=1, the serial I/O starts sending data at the rising edge (Note 1) of RxDi
Note 1: The falling edge of RxDi when IOPOL=0; the rising edge of RxDi when IOPOL=1.
Note 2: TheTransmit condition must be met before the falling edge (Note 1) of RxD.
This diagram applies to the case where IOPOL=1 (reserved).
Oct 16, 2006
Transmission enable condition is met
(Note 2)
page 155 of 264
Input to TAj
ST
ST
ST
D0
D0
ST
IN
D0
D0
D1
D1
D1
D2
D1
D2
D2
D2
D3
D3
If ABSCS=1, bus collision is determined
when timer Aj (one-shot timer mode) underflows.
D3
D3
D4
D4
D4
D4
D5
D5
D5
D5
D6
D6
If ACSE bit=1, (automatically
clear when bus collision occurs),
the TE bit is cleared to “0”
(transmission disabled) when
the UiBCNIC register’s IR bit=1
(unmatching detected).
D6
D6
D7
D7
D7
D7
D8
D8
D8
D8
(i=0 to 3)
SP
SP
SP
IE mode
SP