M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 34

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Oscillation
R/W signal, address bus, data bus, CS
ALE signal, HLDA, programmable I/O ports
Internal peripheral circuits
Table 1.19. Microcomputer status in ready state (Note)
Figure 1.14. Example of RD signal extended by RDY signal
Note: The RDY signal cannot be received immediately before a software wait.
Oct 16, 2006
The ALE signal
The RDY signal
The ALE signal can be used by an external device to latch the address from the address bus. This signal
indicates when the address on the bus is valid. Latch the address when the ALE signal falls.
RDY is a signal that facilitates access to an external device that requires long access time. As shown in Figure
1.14, if an "L" is input to the RDY at the BCLK falling edge, the bus turns to the wait state. If an "H" is being input
to the RDY pin at the BCLK falling edge, the bus cancels the wait state. Table 1.19 shows the state of the
microcomputer with the bus in the wait state. Figure 1.15 is an example of the RD signal prolonged by the RDY
signal.
The RDY signal is valid when accessing the external area during the bus cycle in which bits 4 to 7 of the chip
select control register (address 0008
7 of the chip select control register (address 0008
when not used.
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Item
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RD
RDY
BCLK
CS
(i=0 to 3)
i
: Wait using software
: Wait using RDY signal
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Accept timing of RDY signal
16
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) are set to "0". The RDY signal is invalid when setting "1" to all bits 4 to
tsu(RDY - BCLK)
On
Maintain status when RDY signal received
On
16
), but the RDY pin should still be connected properly as it is
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Status
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Processor Mode
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