M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 68

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.41. Switching condition of INT interrupt request
Rev.2.00
REJ03B0005-0200
The NMI interrupt
External interrupt
The NMI interrupt can not be disabled. Be sure to connect NMI pin to Vcc with a pull-up resistor if unused. Do not go into
stop mode when the NMI pin set to "L".
The NMI pin also serves as P8
value to be read. Reading this pin is only to be used for establishing the pin level when the NMI interrupt is input.
Do not reset the CPU with the input to the NMI pin in the "L" state.
Do not attempt to go into stop mode when the input to the NMI pin is in "L" state. When the input to the NMI is in "L" state,
CM10 is fixed to "0" thereby refusing to go into stop mode.
Do not attempt to go into wait mode when the input to the NMI pin is in "L" state. When the input to the NMI pin is in"L"
state, the CPU stops but the oscillation does not. This action does not save power. When this occurs, the CPU is
returned to the normal state by a later interrupt.
Signals input to the NMI pin require an "L" level of (2 clocks + 300nS) or more from the operation clock of the CPU.
Either an "H" or "L" level of at least 250 ns width is necessary for the signal input to pins INT0 to INT2 regardless of the
CPU operation clock.
When the polarity of the INT0 to INT2 pins is changed, the interrupt request bit is sometimes set to "1". After changing
the polarity, reset the interrupt request bit to "0". Figure 1.41 shows the procedure for changing the INT interrupt generate
factor.
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Oct 16, 2006
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page 66 of 264
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Note: Execute the settings individually. Do not execute two or more settings simultaneously.
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5
, which is exclusively an input. Reading the contents of the P8 register allows the pin
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Set the interrupt priority level to level 0
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Clear the interrupt enable flag to "0"
Clear the interrupt request bit to "0"
Set the interrupt priority level 1 to 7
(Enable the INT i interrupt requests)
Set the interrupt enable flag to "1"
Set the polarity select bit
(Disable
(Disable interrupt)
(Enable interrupt)
INT i
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interrupt)
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Interrupts