M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 63

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Table 1.34. Change of IPL state when interrupt request are accepted
Rev.2.00
REJ03B0005-0200
Reset
NMI
DBC
Watchdog timer
Single step
Address match
Software interrupt
Flag changes
When an interrupt request is received, the stack pointer select flag (U flag) changes to "0" and the flag register (FLG) and
program counter (PC) are saved to the stack area indicated by the interrupt stack pointer (ISP). Thereafter, the interrupt
enable flag (I flag) and debug flag (D flag) change to "0" and the processor interrupt priority level (IPL) at the flag register
(FLG) is replaced by the priority level of the received interrupt. However, when interrupt requests are received for
software interrupts 32 to 63, the flag register (FLG) and program counter (PC) are saved to the stack shown by the stack
pointer select flag (U flag) at the time the interrupt was received. The stack pointer select flag (U flag) does not change.
The value of the processor interrupt priority level (IPL) in the flag register (FLG) differs in the case of reset, NMI, DBC,
watchdog timer, single-step, address-match, BRK instruction, overflow, and undefined instruction interrupts. Table
1.34 shows how the IPL changes when interrupt requests are received.
Oct 16, 2006
Interrupt
page 61 of 264
Le vel 0 ( 000
Le vel 7 ( 111
Does not change
Le vel 7 ( 111
Does not change
Does not ch ange
Does not change
2
2
2
), i s set
), i s set
), is set
Change of IPL
Interrupts
______
_______