M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 149

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
UARTi Special Mode Register (UiSMR)
Bit 0 is the I
SCLi clock input/output pin and port. A delay circuit is added to SDAi transmission output, therefore after SCLi is at
"L" level, SDAi output changes. In I
content of the port direction register. SDAi transmission output is initially set to port in this mode. Furthermore, interrupt
factors for the bus collision detection interrupt and UARTi transmission interrupt change respectively to the start/stop
condition detection interrupts, acknowledge non-detection interrupt and acknowledge detection interrupt.
The start condition detection interrupt is generated when the falling edge at the SDAi pin is detected while the SCLi
pin is in "H" state. The stop condition detection interrupt is generated when the falling edge at the SDAi pin is detected
while the SCLi pin is in the "H" state.
The acknowledge non-detect interrupt is generated when the "H" level at the SDAi pin is detected at the 9th rise of
the transmission clock. The acknowledge detect interrupt is generated when the "L" level at the SDAi pin is detected
at the 9th fall of the transmission clock. Also, DMA transfer can be started when the acknowledge is detected if UARTi
transmission is selected as the DMAi request factor.
Bit 1 is the arbitration detection flag control bit. Arbitration detects a conflict between data transmitted at SCLi rise and
data at the SDAi pin. This detect flag is allocated to bit 11 in UARTi transmit buffer register (addresses 036F
033F
be selected to update the flag in units of bits or bytes. When this bit is set to "1", update is set to units of byte. If a conflict
is still detected, the arbitration lost detect flag control bit will be set to "1" at the 9th rise of the clock. When updating in
units of byte, always clear ("0" interrupt) the arbitration lost detect flag control bit after the first byte has been acknowl-
edge but before the next byte starts transmitting.
Bit 2 is the bus busy flag. It is set to "1" when the start condition is detected, and reset to "0" when the stop condition is
detected.
Bit 3 is the SCLi L synchronization output enable bit. When this bit is set to "1", the port data register is set to "0" in sync
with the "L" level at the SCLi pin.
Bit 4 to Bit 6 : These are not used in I
16
Oct 16, 2006
, 032F
2
16
C mode select bit 1. When set to "1", ports operate respectively as the SDAi data transmit/receive pin,
, 02FF
page 147 of 264
16
). It is set to "1" when a conflict is detected. With the arbitration lost detect flag control bit, it can
2
C master mode, port (SCLi) is designed to read pin level regardless of the
2
C bus interface mode. See "IE mode" section.
I
2
C Bus interface mode
16
, 02EF
16
,