M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 77

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
AUTO_SET is enabled and continuous transfer mode disabled:
AUTO_SET and continuous transfer mode are enabled:
Double Buffer Mode:
Single Buffer Mode:
Double Buffer Mode:
Single Buffer Mode:
The CPU writes a "1" to the SET_IN_BUF_RDY bit of the corresponding EPx IN CSR after the CPU finishes writing a data
set up to its buffer size to the buffer (updates the IN_BUF_STS1 & IN_BUF_STS0 flags). The USB FCU sends out data
packets equal to the MAXP size one at a time, except for the last packet if the data in the buffer is not a multiple of the
MAXP, the USB FCU sends a short packet.
• If the buffer is immediately available to accept another data set, the buffer status flags transition from 00
• If the buffer is not available to accept another data set, the buffer status flags transition from 01
The USB FCU updates the buffers status flags after a data set has been successfully transmitted to the host.
• If the buffer has one more data set in it, the buffer status flags transition from 11
• If the buffer has no more data set in it, the buffer status flags transition from 01
After the CPU writes a data packet equal to the MAXP size to the buffer, the USB FCU updates the corresponding EPx
IN CSR’s IN_BUF_STS1 & IN_BUF_STS0 flags from 00
SET_IN_BUF_RDY bit. The USB FCU updates the buffer status flags from 11
successfully transmitted to the host.
If the data packet is less than the MAXP size, the CPU must write "1" to the SET_IN_BUF_RDY bit to signify the data
packet is ready to send.
After the CPU writes a data packet equal to its MAXP size to the buffer, the USB FCU updates the corresponding EPx
IN CSR’s IN_BUF_STS1 & IN_BUF_STS0 flags.
• If the buffer is immediately available to accept another data packet, the buffer status flags transition from 00
• If the buffer is not available to accept another data packet, the buffer status flags transition from 01
The USB FCU updates the buffers status flags after a data packet has been successfully transmitted to the host.
• If the buffer has one more data packet in it, the buffer status flags transition from 11
• If the buffer has no more data packet in it, the buffer status flags transition from 01
• If the data packet is less than the MAXP size, the CPU must write "1" to the SET_IN_BUF_RDY bit to signify the data
packet is ready to send.
After the CPU writes a data set equal to the buffer size to the buffer, the USB FCU updates the corresponding EPx IN
CSR's IN_BUF_STS1 & IN_BUF_STS0 flags from 00
SET_IN_BUF_RDY bit. The USB FCU sends out data packets equal to the MAXP size one at a time, except for the last
packet if the data set in the buffer is not a multiple of its MAXP, the USB FCU sends a short packet. The USB FCU
updates the buffer status flags from 11
If the data set is less than the buffer size, the CPU must write “1” to the SET_IN_BUF_RDY bit to signify the data set is
ready to send.
Oct 16, 2006
page 75 of 264
2
to 00
2
after the data set has been successfully transmitted to the host.
2
2
to 11
to 11
2
2
automatically without the CPU writing "1" to the
automatically without the CPU writing "1" to the
2
to 00
2
2
to 00
to 01
2
2
2
to 00
after the data packet has been
to 01
2
.
2
.
2
.
2
Universal Serial Bus
.
2
to 11
2
to 11
2
.
2
2
to 01
.
2
to 01
2
.
2
.