M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 58

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Interrupt Enable Flag (I flag)
Interrupt Request Bit
Interrupt Sequence
The interrupt enable flag (I flag) controls the enabling and disabling of maskable interrupts. Setting this flag to "1"
enables all maskable interrupts; setting it to "0" disables all maskable interrupts. This flag is set to "0" after reset.
The interrupt request bit is set to "1" by hardware when an interrupt is requested. After the interrupt is accepted and
jumps to the corresponding interrupt vector, the request bit is set to "0" by hardware. The interrupt request bit can also
be set to "0" by software. (Do not set this bit to "1").
The interrupt sequence, described below, is performed during the period from when an interrupt is accepted to when
the interrupt routine is executed.
If an interrupt occurs during execution of an instruction, the processor determines its priority when the execution of the
instruction is completed, and transfers control to the interrupt sequence from the next cycle. If an interrupt occurs during
execution of either the SMOVB, SMOVF, SSTR or RMPA instruction, the processor temporarily suspends the instruction
being executed, and transfers control to the interrupt sequence.
The processor carries out the following in sequence after an interrupt request:
(1) CPU gets the interrupt information (the interrupt number and interrupt request level) by reading address 00000
(2) Saves the contents of the flag register (FLG) as it was immediately before the start of interrupt sequence in
the temporary register (Note) within the CPU.
(3) Sets the interrupt enable flag (I flag), the debug flag (D flag), and the stack pointer select flag (U flag) to "0" (the U flag,
however does not change if the INT instruction, in software interrupt numbers 32 through 63, is executed).
(4) Saves the contents of the temporary register (Note) within the CPU in the stack area.
(5) Saves the contents of the program counter (PC) in the stack area.
(6) Sets the interrupt priority level of the accepted instruction in the IPL.
After the interrupt sequence is completed, the processor resumes executing instructions from the first address of the
interrupt routine.
Note: This register cannot be utilized by the user.
Oct 16, 2006
Example 1:Using the NOP instruction to keep the program waiting until the interrupt control register is
Example 2:Using the dummy read to keep the FSET instruction waiting
Example 3:Using the POPC instruction to changing the I flag
INT_SWITCH1:
The number of NOP instruction is as follows.
INT_SWITCH2:
INT_SWITCH3:
PM20=1(1 wait) : 2, PM20=0(2 wait) : 3, when using HOLD function : 4.
FCLR
AND.B
MOV.W
FSET
PUSHC
FCLR
AND.B
POPC
FCLR
AND.B
NOP
NOP
FSET
modified
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#00h, 0055h
I
I
I
#00h, 0055h
MEM, R0
I
FLG
I
#00h, 0055h
FLG
; Disable interrupts.
; Set the TA0IC register to “00h”.
;
; Enable interrupts.
; Disable interrupts.
; Set the TA0IC register to “00h”.
; Dummy read.
; Enable interrupts.
; Disable interrupts.
; Set the TA0IC register to “00h”.
; Enable interrupts.
Interrupts
16.