M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 52

IC M16C/24 MCU FLSH 128K 100LQFP

M30245FCGP#U1

Manufacturer Part Number
M30245FCGP#U1
Description
IC M16C/24 MCU FLSH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/20r
Datasheet

Specifications of M30245FCGP#U1

Core Processor
M16C/60
Core Size
16-Bit
Speed
16MHz
Connectivity
I²C, SPI, SSI, UART/USART, USB
Peripherals
DMA, PWM, WDT
Number Of I /o
82
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
R8C
Maximum Speed
16 MHz
Operating Supply Voltage
3.3 V
Data Bus Width
16 Bit
Number Of Programmable I/os
82
Interface Type
USB/UART/I2C/SPI
On-chip Adc
8-chx10-bit
Number Of Timers
5
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
M30245FCGP#U1M30245FCGP
Manufacturer:
RENESAS
Quantity:
102
Company:
Part Number:
M30245FCGP#U1
Manufacturer:
TDK-EPCOS
Quantity:
54 000
Company:
Part Number:
M30245FCGP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
M30245 Group
Interrupts
Figure 1.29. Interrupt classification
Rev.2.00
REJ03B0005-0200
Figure 1.29 lists the types of interrupts.
Software Interrupts
• Maskable: An interrupt that can be enabled or disabled by the interrupt enable flag (I flag) or can have its interrupt
priority changed by the priority level.
• Non-maskable: An interrupt that cannot be enabled or disabled by the interrupt enable flag (I flag) or cannot have its
interrupt priority changed by the priority level.
A software interrupt occurs when executing certain instructions. Software interrupts are non-maskable interrupts.
• Undefined instruction interrupt
An undefined instruction interrupt occurs when executing the UND instruction.
• Overflow interrupt
An overflow interrupt occurs when an executing arithmetic instruction overflows. The instructions that set an O flag when
an overflow occurs are: ABS, ADC, ADCF, ADD, CMP, DIV, DIVU, DIVX, NEG, RMPA, SBB, SHA, SUB
• BRK interrupt
A BRK interrupt occurs when executing the BRK instruction.
• INT interrupt
An INT interrupt occurs when specifying one of the software interrupt numbers 0 through 63 and executing the INT
instruction. Software interrupt numbers 0 through 31 are assigned to peripheral I/O interrupts, so executing the INT
instruction executes the same interrupt routine as the peripheral I/O interrupt.
The stack pointer (SP), used for the INT interrupt, is dependent on which software interrupt number is selected.
As far as software interrupt numbers 0 through 31 are concerned, the microcomputer saves the stack pointer assign-
ment flag (U flag) when it accepts an interrupt request. The U flag is set to "0"” selecting the interrupt stack pointer then
the interrupt sequence is executed. When returning from the interrupt routine, the U flag is returned to its previous state
before accepting the interrupt request.
As far as software numbers 32 through 63 are concerned, the stack pointer does not change.
Oct 16, 2006
Note : PeripheralI/Ointerruptsaregeneratedbytheperipheralfunctionsbuiltintothemicrocomputersystem.
page 50 of 264
Interrupt
Software
Hardware
Peripheral I/O (Note)
Special
Undefined instruction (UND instruction)
Overflow (INTO instruction)
BRK instruction
INT instruction
Address match
Reset
NMI
DBC
Watchdog timer
Single step
Interrupts

Related parts for M30245FCGP#U1