M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 142

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.99. Typical receive timing in UART mode
Figure 1.100. Timing for switching serial data logic
Rev.2.00
REJ03B0005-0200
Serial data logic switch function
When the data logic select bit (bit 6 of address 03AD
writing to the transmission buffer register or reading the reception buffer register. Figure 1.100 shows an example of
timing for switching serial data logic.
Transfer clock
Receive
complete flag
BRGi count
source
Receive enable bit
RxDi
RTSi
Receive interrupt
request bit
Oct 16, 2006
Transfer clock
Example of receive timings when transfer data is 8 bits long (parity disabled, one stop bit)
• When LSB first, parity enabled, one stop bit
(no reverse)
(reverse)
TxD
TxD
i
i
page 140 of 264
"1"
"0"
"1"
"0"
"H"
"L"
"1"
"0"
"H"
"H"
"H"
"L"
"L"
"L"
The above timing applies to the following settings :
Reception triggered when transfer clock
is generated by falling edge of start bit
•Parity is disabled.
•One stop bit.
•RTS function is selected.
Start bit
ST
ST
Sampled "L"
D0
D0
D1
D1
Cleared to "0" when interrupt request is accepted, or cleared by software
16
D2
D2
, 036D
D
0
Receive data taken in
Transferred from UARTi receive register to
UARTi receive buffer register
D3
D3
16
, 033D
Becomes "L" by reading the receive buffer
D4
D4
Clock asynchronous serial I/O (UART) mode
16
D
1
, 032D
D5
D5
D
D6
D6
7
16
) is set to "1", data is inverted when
D7
D7
Stop bit
ST : Start bit
P : Parity bit
SP : Stop bit
P
P
SP
SP