M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 42

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Clock Control
Rev.2.00
REJ03B0005-0200
Main clock
Subclock
Peripheral function clock (f
BCLK
The main clock is generated by the main clock oscillation circuit. After a reset, this clock is divided by 8 to produce the
BCLK. The clock can be stopped using the main clock stop bit (bit 5 at address 0006
switching the operating clock source of CPU to the subclock, reduces the power dissipation.
After the oscillation of the main clock oscillation circuit has stabilized, the drive capacity of the main clock oscillation
circuit can be reduced using the X
of the main clock oscillation circuit reduces power dissipation. This bit changes to "1" when shifting from high-speed/
medium-speed mode to stop mode and at a reset. When shifting from low-speed/low power dissipation mode to stop
mode, the value before stop mode is retained.
The subclock is generated by the subclock oscillation circuit. No subclock is generated after a reset. After oscillation is
started using the port Xc select bit (bit 4 at address 0006
system clock select bit (bit 7 at address 0006
before switching.
After the oscillation of the subclock oscillation circuit has stabilized, the drive capacity of the subclock oscillation circuit
can be reduced using the X
the subclock oscillation circuit reduces the power dissipation. This bit changes to "1" when changing to stop mode and
at a reset.
The BCLK is the clock that drives the CPU, and is equal to fc or the clock that is derived by dividing the main clock by 1,
2, 4, 8, or 16. The BCLK is derived by dividing the main clock by 8 after a reset. The BCLK signal can be output from the
BCLK pin (P5
microprocessor modes.
The main clock division select bit 0 (bit 6 at address 0006
speed to stop mode and at reset. When shifting from low-speed/low power dissipation mode to stop mode, the value
before stop mode is retained.
The clock for the peripheral devices is derived from the main clock or by dividing it by 1, 8, or 32. The peripheral function
clock is stopped by stopping the main clock or by setting the WAIT peripheral function clock stop bit (bit 2 at 0006
"1" and then executing a WAIT instruction.
fc
This clock is derived by dividing the subclock by 32. It is used for the Timer A counts.
This clock has the same frequency as the subclock. It is used for the BCLK and for the watchdog timer.
f
This clock provides a 48 MHz signal required for USB operation. It is derived from the Frequency Synthesizer circuit.
fc
USB
32
Oct 16, 2006
3
) by use of the BCLK output disable bit (bit 7 at address 0004
page 40 of 264
1
CIN
, f
8
-X
, f
COUT
32
IN
-X
, f
1SIO2
OUT
drive capacity select bit (bit 3 at address 0006
drive capacity select bit (bit 5 at address 0007
, f
8SIO2
16
). However, be sure that the subclock oscillation has fully stabilized
, f
32SIO2
16
, f
16
), the subclock can be selected as the BCLK by using the
AD
) changes to "1" when shifting from high-speed/medium-
)
16
) in the memory expansion and the
16
). Reducing the drive capacity of
16
16
). Reducing the drive capacity
). Stopping the clock, after
System Clock
16
) to