M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 95

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
USB Endpoint x OUT CSR (x = 1 to 4)
The USB Endpoint x OUT CSR (Control and Status Register), shown in Figure 1.61, contains control and status
information for the respective OUT EP 1-4.
• OUTxCSR0 (OUT_BUF_STS0) and OUTxCSR1 (OUT_BUF_STS1):
Two status flags, indicate the current status of the OUT buffer. The buffer status flags are updated when one of the
following events occurs:
1. The USB FCU successfully receives a data set from the host.
2. The CPU unloads a data set from the buffer (writes a "1" to CLR_OUT_BUF_RDY).
3. The CPU writes a "1" to the FLUSH bit.
• OUTxCSR2 (OVER_RUN):
A status flag, "1" indicates an over run has occurred in an isochronous data transfer. The USB FCU updates this flag to
a "1" at the beginning of an OUT token when two data packets are already present in the buffer.
• OUTxCSR3 (FORCE_STALL):
A status flag, "1" indicates that the USB FCU detected a Packet size larger than MAXP violation. The USB FCU returns a
STALL as a handshake packet for the current transaction.
• OUTxCSR4 (DATA_ERR):
A status flag, "1" indicates a data error (bit stuffing or CRC error) has occurred in an OUT isochronous data packet.
• OUTxCSR5 (CLR_OUT_BUF_RDY):
The CPU writes a "1" to this bit after unloading a data set from the buffer. The CPU can only unload data from the buffer
and set this bit when OUTxCSR1 (OUT_BUF_STS1) is a "1".
• OUTxCSR6 (CLR_OVER_RUN):
The CPU writes a "1" to this bit to clear the OVER_RUN status flag.
• OUTxCSR7 (CLR_FORCE_STALL):
The CPU writes a "1" to this bit to clear the FORCE_STALL status flag.
• OUTxCSR8 (CLR_DATA_ERR):
The CPU writes a "1" to this bit to clear the DATA_ERR status flag.
• OUTxCSR9 (TOGGLE_INIT):
The CPU writes a "1" to this bit to initialize the data sequence, and force the next packet’s data PID to a DATA0 for
reception.
• OUTxCSR10 (FLUSH):
The CPU writes a "1" to this bit to flush the OUT buffer. This bit must only be set to a "1" when the OUT_BUF_STS1 flag
is a "1".
• When there is one data set in the OUT buffer, a flush causes the OUT buffer to be empty.
• When there are two data sets in the OUT buffer, a flush causes the older packet to be flushed from the OUT buffer.
The USB FCU updates the buffer status flags the same way as a data set is unloaded from the host when it sees a
FLUSH. Setting the FLUSH bit during reception could produce unpredictable results.
Oct 16, 2006
page 93 of 264
Universal Serial Bus