M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 60

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.34. Interrupt sequence timing
Rev.2.00
REJ03B0005-0200
Returning from an Interrupt Routine
Interrupt priority
____________
RESET > NMI > DBC > Watchdog Timer > Peripheral I/O > Single step > Address match
Interrupt Priority Level Select Bit and Processor Interrupt Priority Level (IPL)
Executing the REIT instruction at the end of an interrupt routine restores the contents of the flag register (FLG) as it was
immediately before the start of the interrupt sequence and the contents of the program counter (PC), both of which were
saved in the stack area. Then control returns to the program that was being executed before the acceptance of the
interrupt request, so that the suspended process resumes.
Return the other registers that were saved by software within the interrupt routine using the POPM instruction or a
similar instruction before executing the REIT instruction.
The order of priority when two or more interrupts are generated simultaneously is determined by both hardware and
software.
The interrupt priority levels determined by hardware are:
The interrupt priority levels determined by software are set in the interrupt control registers.
When two or more interrupts are generated simultaneously, the interrupt with the higher software priority is selected.
However, if the interrupts have the same software priority level, the interrupt is selected according to the hardware
priority set in the circuit.
The selected interrupt is accepted only when the priority level is higher than the processor interrupt priority level (IPL) in
the flag register (FLG) and the interrupt enable flag (I flag) is "1" Note that the reset, NMI, DBC, watchdog timer, single-
step, address-match, BRK instruction, overflow, and undefined instruction interrupts are accepted regardless of the
interrupt enable flag (I flag).
Set the interrupt priority level using the interrupt priority level select bits, which consists of three interrupt control register
bits. When an interrupt request occurs, the interrupt priority level is compared with the IPL of the CPU flag register. The
interrupt is enabled only when the priority level of the interrupt is higher than the IPL. Therefore, setting the interrupt
priority level to "0" disables the interrupt.
Oct 16, 2006
_______
BCLK
Internal
Address bus
Internal
Data bus
R
W
The indeterminate segment is dependent on the queue buffer.
If the queue buffer is ready to take an instruction, a read cycle occurs.
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1
Address 0000
2
information
Interrupt
3
4
5
Indeterminate
Indeterminate
Indeterminate
6
7
8
9
SP-2
SP-2 contents
10
11
SP-4 contents
SP-4
12
vec
vec
contents
______
vec + 2
vec + 2
contents
_______
PC
Interrupts