M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 54

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Interrupt Routine
Figure 1.30. Format for specifying interrupt vector addresses
Table 1.27. Interrupt vectors with fixed addresses
Note: Interrupts used for debugging purposes only.
Rev.2.00
REJ03B0005-0200
Undefined instruction
Overflow
BRK instruction
Address Match
Single Step (Note)
Watchdog timer
DBC (Note)
NMI
Reset
Interrupt vector tables
Fixed vector tables
Interrupt source
1If an interrupt request is accepted, program execution branches to the interrupt routine set in the interrupt vector table.
Set the first address of the interrupt routine in each vector table. Figure 1.30 shows the format for specifying the address.
Two types of interrupt vector tables are available - fixed vector table in which addresses are fixed and variable vector
table in which addresses can be varied by the setting.
The fixed vector table is a table in which addresses are fixed. The vector tables are located in an area extending from
FFFDC
table. Table 1.27 shows the interrupts assigned to the fixed vector tables and addresses of vector tables.
Oct 16, 2006
16
to FFFFF
16
page 52 of 264
. One vector table comprises four bytes. Set the first address of interrupt routine in each vector
Address(L) to Address(H)
FFFDC
FFFE0
FFFE4
FFFE8
FFFEC
FFFF0
FFFF4
FFFF8
FFFFC
Vector table addresses
Vector address + 0
Vector address + 1
Vector address + 2
Vector address + 3
16
16
16
16
16
16
16
16
16
to FFFF3
to FFFF7
to FFFFB
to FFFE3
to FFFE7
to FFFEB
to FFFFF
to FFFEF
to FFFDF
16
16
16
16
16
16
16
16
16
MSB
Interrupt on UND instruction
Interrupt on INTO instruction
If the vector is filled with FF
the address shown by the vector in the variable vector table
There is an address-matching interrupt enable bit
Do not use
Do not use
External interrupt by NMI pin
0 0 0 0
0 0 0 0
Low address
Mid address
address
0 0 0 0
High
LSB
Remarks
16
, program execution starts from
Interrupts