M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 167

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Table 1.55. USB FIFO sequence operation
Second Word Write
Third Word Write
First Word Write
Precautions
OPERATION
The USB FIFO is read using word accesses and each word is written to the transmit buffer. Table 1.55 lists the USB
FIFO sequence operation. Note that DB refers to the MCU data bus.
Data are placed in the buffer from the least significant byte to the most significant byte with the left buffer written first.
If the write operation is a word, the lower order data bus bits (DB
higher order data bus bits (D
The same operation sequences occur for the receive buffer read. On a byte access, data are placed on the bus with
the most significant byte first. If the access is a word read, the lower order data bus bits (DB
more significant.
•
•
- SCKP=0 (falling edge) : within 3 BCLK cycles from the rising edge of SCK
- SCKP=1 (rising edge) : within 3 BCLK cycles from the falling edge of SCK
For flash memory version SSI transmission data must be latched as the following timing by a receiver.
Entering wait mode with the SSI active can produce unpredictable data transfers. Make sure to disable the SSI
transmitter and receiver before entering wait mode, and re-enable the transmitter and receiver after exiting wait mode.
Oct 16, 2006
page 165 of 264
DB
(L23-L16)
Byte 2
7
- DB
15
-DB
0
8
). This is compatible with the USB.
Left Buffer
DB
(L15-L8)
Byte 1
15
- DB
8
DB
Byte 0
(L7-L0)
7
- DB
7
0
-DB
0
DB
) are treated as more significant than the
(R23-R16)
Byte 2
15
- DB
8
Right Bufferi
DB
(R15-R8)
Byte 1
Serial Sound Interface
7
7
- DB
-DB
0
0
) are treated as
DB
Byte 0
(R7-R0)
15
- DB
8