M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 107

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Transfer modes
DMA enable bit
DMA request bit
Single transfer mode
Repeat transfer mode
DMA transfer occurs until the tranfer counter underflows. Afterward, the DMA becomes inactive.
The DMA remains active even after the transfer counter underflows. The transfer counter and forward direction address
pointer are reloaded after each transfer counter underflow. The DMA becomes inactive when "0" is written to the DMA
enable bit.
Setting the DMA enable bit to "1" makes the DMAC active. If data transfer starts immediately after the DMAC is turned
active, the following operations are carried out:
(1) Reloads the value of either the source pointer or the destination pointer - the one specified for the forward direction
- to the forward direction address pointer.
(2) Reloads the value of the transfer counter reload register to the transfer counter.
Thus writing "1" to the DMA enable bit with the DMAC being active carries out the operations given above, so the DMAC
operates again from the initial state at the instant "1" is written to the DMA enable bit.
The DMAC can generate a DMA transfer request signal triggered by a factor chosen in advance out of DMA request
causes for each channel (DMiSL registers).
DMA request causes include the following.
• Internal causes triggered by using the interrupt request signals from the built-in peripheral functions and software
DMA request all controlled by software.
• External causes effected by utilizing the input from external interrupt signals.
For the selection of DMA request causes, see the descriptions of the DMAi request cause select registers.
The DMA request bit turns to "1" if the DMA transfer request signal occurs regardless of the DMAC's state (regardless
of whether the DMA enable bit is set "1" or to "0"). It turns to "0" immediately before data transfer starts.
In addition, this bit can be set to "0" by software, but it cannot be set to "1".
There can be instances in which a change in the DMA request cause selection bits causes the DMA request bit to turn
to "1". Make sure to set the DMA request bit to "0" after the DMA request cause selection bits are changed.
The DMA request bit turns to "1" if a DMA transfer request signal occurs, and turns to "0" immediately before data transfer
starts. If the DMAC is active, data transfer starts immediately, so the value of the DMA request bit, if read by software,
turns out to be "0" in most cases. To examine whether the DMAC is active, read the DMA enable bit.
The timing changes of the DMA request bit are discussed in the following section.
Oct 16, 2006
page 105 of 264
DMA