M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 36

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Note 1: When using the RDY signal, always set this bit to "0".
Note 2: Set the CSxW bit to 0 before setting these bits. Also, when setting the CSxW bit to 1, be sure to reset these bits to '00 2 ' first.
External memory area
SFR
Internal ROM/RAM
Table 1.22. Software waits and bus cycles
Software wait
A software wait of one to three BCLK cycles can be inserted by setting bits 4 to 7 of the chip select control
register (address 0008
Software waits can be set independently for each of the 4 chip select memory areas. Bits 4 to 7 of the chip select
control register correspond to chip selects CS0 to CS3. When one of these bits is set to "1", the read bus cycle
is executed in one BCLK cycle and the write bus cycle is executed in two BCLK cycles. When set to "0", the read
and write bus cycles are executed in two, three or four BCLK cycles, depending on the settings in the chip select
expansion register. The bits in the chip select expansion register are only valid when the corresponding bit in
the chip select control register is set to "0". When the bits in the chip select control register are set to "1", the
corresponding bits in the chip select expansion register must be set to "00
register and chip select expansion register default to "0" after the microcomputer has been reset.
When the user is using the RDY signal, the relevant bit in the chip select control register’s bits 4 to 7 must be
set to "0".
The SFR area is always accessed in two BCLK cycles regardless of the setting of these control bits.
Table 1.22 shows the software waits and bus cycles. Figures 1.15 and 1.16 show example bus timing when
using software waits.
Oct 16, 2006
Area
page 34 of 264
16
) and the bits in the chip select expansion register (address 001B
________
CSxW
(Note 1)
Invalid
Invalid
0
0
0
0
1
_______
_______
CSExW
(Note 2)
Invalid
Invalid
00
01
10
11
00
2 BCLK cycles
3 BCLK cycles
4 BCLK cycles
2 BCLK cycles
1 BCLK cycle
1 BCLK cycle
2
". The bits in the chip select control
Inhibited
Read
Bus Cycles
Processor Mode
16
2 BCLK cycles
3 BCLK cycles
4 BCLK cycles
2 BCLK cycles
2 BCLK cycles
1 BCLK cycle
).
Inhibited
Write