M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 53

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Hardware Interrupts
Rev.2.00
REJ03B0005-0200
Hardware interrupts are classified into two types - special interrupts and peripheral I/O interrupts.
Special interrupts
Peripheral I/O interrupts
Special interrupts are non-maskable interrupts.
• Reset
Reset occurs if an "L" is input to the RESET pin.
• NMI interrupt
An NMI interrupt occurs if an "L" is input to the NMI pin.
• DBC interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances.
• Watchdog timer interrupt
Generated by the watchdog timer.
• Single-step interrupt
This interrupt is exclusively for the debugger, do not use it in other circumstances. With the debug flag (D flag) set to "1",
a single-step interrupt occurs after one instruction is executed.
• Address match interrupt
An address match interrupt occurs immediately before the instruction held in the address indicated by the address
match interrupt register is executed with the address match interrupt enable bit set to "1". If an address other than the
first address of the instruction in the address match interrupt register is set,
A peripheral I/O interrupt is generated by one of the built-in peripheral functions. Built-in peripheral functions are
dependent on classes of products, so the interrupt factors are also dependent on classes of products. The interrupt
vector table is the same as the one for software interrupt numbers 0 through 31 the INT instruction uses. Peripheral I/
O interrupts are maskable interrupts.
• Bus collision detection interrupt
This is an interrupt that the serial I/O bus collision detection generates.
• DMA0 through DMA3 interrupt
These are interrupts the DMA generates.
• Key-input interrupt
A key-input interrupt occurs if an "L" is input to any of the KI
• A/D conversion interrupt
This is an interrupt that the A/D converter generates.
• UART0, UART1, UART2, UART3 transmit / NACK / SSI0, SSI1 transmit interrupt
These are interrupts that the serial I/O, I
• UART0, UART1, UART2, UART3 receive / ACK / SSI0, SSI1 receive interrupt
These are interrupts that the serial I/O, I
• Timer A0 interrupt through Timer A4 interrupt
These are interrupts that Timer A generates
• INT0 through INT2 interrupt
An INT interrupt occurs if either a rising edge or a falling edge or both edges are input to one of the INT pins.
• USB interrupts (EP0, Suspend, Resume, SOF, Reset, USB Function)
These are interrupts that are generated from USB.
• VBus Detect interrupt
This interrupt is generated from the USB VBus detection circuitry.
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2
2
C, and SSI generate.
C, and SSI generate.
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1
to KI
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7
pins.
Interrupts