M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 15

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Figure 1.6. Central processing unit register
Central Processing Unit
The CPU has a total of 13 registers shown in Figure 1.6. Seven of these registers (R0, R1, R2, R3, A0, A1, and
FB) come in two sets; therefore, these have two register banks.
Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)
Address registers (A0 and A1)
Frame base register (FB)
Oct 16, 2006
Data registers (R0, R1, R2, and R3) are configured with 16 bits, and are used primarily for transfer and
arithmetic/logic operations.
Registers R0 and R1 each can be used as separate 8-bit data registers, high-order bits as (R0H/R1H),
and low-order bits as (R0L/R1L). In some instructions, registers R2 and R0, as well as R3 and R1 can
use as 32-bit data registers (R2R0/R3R1).
Address registers (A0 and A1) are configured with 16 bits, and have functions equivalent to those of data
registers. These registers can also be used for address register indirect addressing and address
register relative addressing.
In some instructions, registers A1 and A0 can be combined for use as a 32-bit address register (A1A0).
Frame base register (FB) is configured with 16 bits, and is used for FB relative addressing.
R0
R1
R2
R3
A0
A1
FB
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(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
b15
b15
b15
b15
b15
b15
Note: These registers consist of two register banks.
b15
H
H
b8 b7
b8 b7
L
L
b0
b0
b0
b0
b0
b0
b0
Data
registers
Address
registers
Frame base
registers
IPL
PC
INTB
b19
b19
USP
ISP
SB
FLG
H
b15
b15
b15
U
b15
I
O
B
L
S
Z
D
C
b0
b0
b0
b0
b0
b0
Program counter
Interrupt table
register
User stack pointer
Interrupt stack
pointer
Static base
register
Flag register
Central Processing Unit