M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 103

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Rev.2.00
REJ03B0005-0200
Note: DMA transfer is not effective to any interrupts. DMA transfer is not affected by the interrupt enable flag (I flag) or
by the interrupt priority level.
No. of channels
Transfer memory space
Maximum No. of bytes transferred
DMA request factors (Note)
Channel priority
Transfer unit
Transfer address direction
Transfer mode
DMA interrupt request generation
timing
Active
Inactive
Forward address pointer and reload
timing for transfer counter
Writing to register
Reading the register
Table 1.37. DMAC specifications
Oct 16, 2006
Item
page 101 of 264
4 (cycle steal method)
128K bytes (with 16-bit transfers) or 64K bytes (with 8-bit transfers)
High to low priority: DMA0, DMA1, DMA2, DMA3
8 bits or 16 bits
Forward/fixed (forward direction cannot be specified for both source and
destination simultaneously)
When an underflow occurs in transfer counter
When data transfer starts immediately after turning DMAC active, or when the
transfer counter underflows in repeat transfer mode, the value of the source
pointer or destination pointer (whichever is specified for forward direction) is
reloaded to the forward direction address pointer, and the value of the transfer
counter reload register is reloaded to the transfer counter.
Can be read at any time. However, when the DMA enable bit is "1", reading the
register set-up as the forward register is the same as reading the value of the
forward address pointer.
Serial Sound Interface 0-1 transmit and receive interrupt
USB triggers, selectable by endpoint
enable bit is "0".
DM Atriggers
Repeat transfer mode
When the DMA enable bit is set to "0", the DMAC is inactive
Registers specified for forward direction transfer are always write enabled.
Registers specified for fixed address transfer are write-enabled when the DMA
From a fixed address to any address in the 1M bytes space
From a fixed address to a fixed address (note that DMA related registers
[0020
Falling edge of INT0, INT1, INT2 or both edges
Timer A0 to Timer A4 interrupt requests
UART0-3 transfer and receive interrupt requests
A/D conversion interrupt request
Software triggers
Single transfer mode
When the DMA enable bit is set to "1", the DMAC is active.
When the DMAC is active, data transfer starts each time the DMA transfer
After the transfer counter underflows in single transfer mode.
From any address in the 1M bytes space to a fixed address
request signal occurs.
After the transfer counter underflows, the DMA enable bit is set to "0"
After the transfer counter underflows, the value of the transfer counter
and the DMAC becomes inactive
reload register is reloaded to the transfer counter. The DMAC remains
active unless a "0" is written to the DMA enable bit.
16
to 003F
16
and 0180
16
Specification
to 019F
16
] cannot be accessed)
DMA