M30245FCGP#U1 Renesas Electronics America, M30245FCGP#U1 Datasheet - Page 192

• Manufacturer Part Number: M30245FCGP#U1
• Description: IC M16C/24 MCU FLSH 128K 100LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/20r

Specifications of M30245FCGP#U1

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, SSI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 82
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -20°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100LQFP
• Family Name: R8C
• Maximum Speed: 16 MHz
• Operating Supply Voltage: 3.3 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 82
• Interface Type: USB/UART/I2C/SPI
• On-chip Adc: 8-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

M30245 Group
Figure 1.143. Port control register
Rev.2.00
REJ03B0005-0200
AND Flash Control Circuit
The AND flash control circuit is used for communicating with external AND type flash memory devices. The AND flash
control circuit can be used only in single-chip mode. This circuit cannot be emulated by ICE. The Port Control Register
(PCR), described by Figure 1.143, is used for overall control of this circuit. Setting bit AFPE to '1' assigns port pins
P0
function, these activated signals are listed in Table 1.66, and described as follows:
Figure 1.132 in the Programmable I/O section shows how the AND flash control circuitry is integrated with the port
control logic for pins P0
0
AND_DATA(7:0) - These signals comprise the bus for input/output communication of data between the CPU
and external flash memory. Upon circuit activation, the port P0 pins function as these signals. The port P0
direction register must be used to setup the direction of the AND_DATA(7:0) bus for input/output operation.
AND_OE - This signal is assigned to pin P1
during each read from flash memory. When OECTRL is '0', AND_OE remains set "L".
AND_WE - This signal is assigned to pin P1
during each write to flash memory. When WECTRL is '0', AND_WE remains set "H".
AND_SC - This signal is assigned to pin P1
output on this signal during each flash memory write. If OECTRL is set to '0' and WECTRL set to '1', every read
from flash memory will cause a "H" pulse to be output. The condition whereby both OECTRL and WECTRL are
set to '1' results in AND_SC remaining set "L".
-P0
Port control register
Oct 16, 2006
b7
7
and P1
b6
b5
b4
0
-P1
b3
2
page 190 of 264
to function as signals necessary to interface with external flash memory. Along with their basic
b2
0
-P0
b1
7
b0
and P1
Bit Symbol
OECTRL
WECTRL
AFPE
Nothing is assigned.
Write "0" when writing to this bit. The value is"0" when read.
PCR0
Symbol
PCR
0
-P1
2
.
AND Flash OE control bit
AND Flash WE control bit
AND Flash port enable bit
Port P1 control register
0
2
1
. With OECTRL set to '1' and WECTRL set to '0', a "H" pulse will be
. Setting bit OECTRL to '1' will output a "L" pulse on this signal
. Setting bit WECTRL to '1' will output a "L" pulse on this signal
Bit Name
0 : When input port, read port input
1 : Read the contents of Port P1
0 : Data read mode enabled
1 : Output disabled
0 : Input disabled
1 : Command/Address mode enabled
0 : P0 & P1(
1 : P0 & P1(
register through input/output port.
level. When output port, read the
contents of Port P1 register.
Address
function
03FF
16
0-2
0-2
Function
) GPI/O function
) AND Flash control
And Flash Control Circuit
When reset
00
O O
O O
R W
O O
16
O O
_
_